7210139

Processor Cluster Architecture and Associated Parallel Processing Methods

PublishedApril 24, 2007
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
9 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of executing a task in parallel on a plurality of processors, the method comprising: (a) storing a sequence of code pages of said task in a common program memory; (b) broadcasting a current code page of said sequence of code pages on a code distribution bus to concurrently load the current code page into a plurality of local memories of the plurality of processors; (c) monitoring the plurality of processors to determine whether all of the processors have completed execution of the current code page from their corresponding local memories; and (d) after all of the processors have finished executing the current code page, repeating (b) and (c) with a next sequential code page of said sequence treated as the current code page, at least until all code pages of the sequence have been executed; whereby each code page of the sequence is executed in parallel by the plurality of processors.

2

2. The method of claim 1 , wherein the method comprises processing a different respective dataset with each of the plurality of processors.

3

3. The method of claim 1 , wherein the task is a voice processing task, and the method comprises processing a plurality of voice data streams in parallel with the plurality of processors.

4

4. The method of claim 1 , wherein each processor executes the current code page from a different respective local memory.

5

5. The method of claim 1 , wherein each of the local memories is shared by two of the processors.

6

6. The method of claim 1 , wherein each code page of said sequence has a size of less than 4K instruction words.

7

7. The method of claim 1 , wherein broadcasts of code pages on the code distribution bus in step (b) are interleaved with broadcasts of code pages of a second task to a second plurality of processors.

8

8. The method of claim 1 , wherein the method is performed entirely within an integrated circuit.

9

9. The method of claim 1 , wherein steps (b)–(d) are performed by a task control processor that executes a control program.

Patent Metadata

Filing Date

Unknown

Publication Date

April 24, 2007

Inventors

Richard F. Hobson
Bill Ressl
Allan R. Dyck

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Cite as: Patentable. “PROCESSOR CLUSTER ARCHITECTURE AND ASSOCIATED PARALLEL PROCESSING METHODS” (7210139). https://patentable.app/patents/7210139

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