Apparatus and Method for Address Bus Power Control

1. A bus agent comprising: a controller coupled to an external bus to cause assertion of a power control signal if an address is to be transferred to a separate bus agent coupled to the external bus, the power control signal to enable a set of input address sense amplifiers of the separate bus agent, prior to the separate bus agent receiving the address, wherein the controller is also to cause de-assertion of the power control signal to disable the sense amplifiers once the address has been received by the separate bus agent.

2. The bus agent of claim 1 , wherein the controller is also to cause the de-assertion of the power control signal to disable the sense amplifiers after the address has been received if no additional address value is scheduled to be sent within a predetermined number of clock periods.

3. The bus agent of claim 1 , wherein the bus agent is a chipset.

4. The bus agent of claim 1 , wherein the bus agent is a memory controller.

5. The bus agent of claim 1 , wherein the separate bus agent is a processor.

6. A bus agent comprising: an interface to a bus, the interface to cause assertion of a power control signal if the bus agent is to place an address on the bus, the power control signal to allow a set of input address sense amplifiers of a separate bus agent on the bus to receive the address, wherein the interface is also to cause the de-assertion of the power control signal to disable the sense amplifiers once the address has been received by the separate bus agent.

7. The bus agent of claim 6 , wherein the interface is also to cause delay of the de-assertion of the power control signal to disable the sense amplifiers after the address has been received if at least one additional address is scheduled to be sent within a predetermined number of clock periods.

8. The bus agent of claim 7 , wherein the predetermined number of clock periods is at least 2 clock periods.

9. The bus agent of claim 6 , wherein the bus agent is a chipset.

10. The bus agent of claim 6 , wherein the bus agent is a memory controller.

11. The bus agent of claim 7 , wherein the separate bus agent is a processor.

12. A bus agent comprising: an input buffer having a set of input address sense amplifiers; and the sense amplifiers are coupled to a power control signal, the sense amplifiers are caused to be enabled to receive an address from an external bus agent in response to assertion of the power control signal by the external bus agent, prior to the bus agent receiving an address.

13. The bus agent of claim 12 , wherein the input address sense amplifiers are caused to be disabled after the bus agent has received the address in response to de-assertion of the power control signal.

14. The bus agent of claim 12 , wherein the bus agent is a processor.

15. The bus agent of claim 12 , wherein the external bus agent is a chipset.

16. The bus agent of claim 12 , wherein the external bus agent is a memory controller.

17. The bus agent of claim 12 , wherein the sense amplifiers are caused to be enabled to receive an address from the external bus agent in response to assertion of the power control signal at least two clock periods prior to the bus agent receiving the address.

18. A method comprising: recognizing, by a bus agent, that an address is to be transferred over a bus; asserting a power control signal to enable a set of input address sense amplifiers of a separate bus agent on the bus, prior to the separate bus agent receiving the address; and de-asserting the power control signal to disable the set of input address sense amplifiers after completion of the address transfer.

19. The method of claim 18 , further comprising delaying the de-asserting of the power control signal to disable the set of input address sense amplifiers after completion of an address transfer if an address is scheduled to be sent to the separate bus agent within a predetermined number of clock periods.

20. The method of claim 18 , wherein the asserting the power control signal includes asserting the power signal at least two clock periods prior to an address delivery period.

21. The method of claim 18 , wherein the method is performed by a chipset.

22. The method of claim 18 , wherein the method is performed by a memory controller.

23. The method of claim 18 , wherein the separate bus agent is a processor.

24. An article comprising a machine readable carrier medium carrying data which, when loaded into a computer system memory in conjunction with simulation routines, provides functionality of a model comprising: a controller, coupled to an external bus, to cause assertion of a power control signal if an address is to be transferred to a separate bus agent coupled to the external bus, the power control signal to enable a set of input address sense amplifiers of the separate bus agent, prior to the separate bus agent receiving the address, wherein the controller is also to cause de-assertion of the power control signal to disable the sense amplifiers once the address has been received by the separate bus agent.

25. The article of claim 24 , wherein the controller is also to cause the de-assertion of the power control signal to disable the sense amplifiers after the address has been received if no additional address value is scheduled to be sent within a predetermined number of clock periods.

26. The article of claim 24 , wherein the bus agent is a chipset.

27. The article of claim 24 , wherein the bus agent is a memory controller.

28. The bus agent of claim 1 , wherein the separate bus agent is a processor.

29. A system comprising: an external bus; a chipset coupled to the external bus, comprising: a controller to cause assertion of a power control signal if an address is to be transferred to a processor, the controller to cause de-assertion of the power control signal to disable the set of input address sense amplifiers after completion of an address transfer; and the processor coupled to the external bus, comprising: an input buffer having a set of input address sense amplifiers, the sense amplifiers are coupled to the power control signal, the sense amplifiers are caused to be enabled to receive an address from the chipset in response to assertion of the power signal, prior to the processor receiving the address.

30. The system of claim 29 , wherein the controller of the chipset is to cause de-assertion of the power control signal to disable the set of input address sense amplifiers after completion of the address transfer and if no address is scheduled to be sent to the requesting agent within a predetermined clock period.