Legal claims defining the scope of protection, as filed with the USPTO.
1. A digital communication system for processing Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line, the system comprising: an open-loop equalizer circuit operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals, the open-loop equalizer circuit comprising: a differential pair defining first and second inputs; a reactive load coupled to the differential pair; and a pair of input follower circuits configured to receive the DVI communication data signals and feedback signals from the reactive load and generate corresponding first and second input signals for the first and second inputs of the differential pair the open-loop equalizer circuit providing a frequency dependent gain that is at or about the inverse of a frequency dependent attenuation caused by the transmission line, the DVI communication data signal being proportionately equalized, and if the open-loop equalizer provides a frequency dependent gain that is greater than the inverse of a frequency dependent attenuation caused by the transmission line, then the DVI communication data signal being proportionately equalized.
2. The system of claim 1 , further comprising: a compensation circuit operable to compensate for intermediate circuitry attenuation of the DVI communication data signals.
3. The system of claim 1 , further comprising: a DDC extension circuit operable to inject a boost current at a receive end of the transmission line during a positive transition in the DDC communication signals.
4. The system of claim 1 , wherein the pair of input follower circuits are further configured to provide unity gain.
5. The system of claim 4 , wherein the input follower circuits comprise: a first operational amplifier configured to receive as input a first DVI communication data signal and to receive a first feedback signal from the reactive load and generate the first input signal applied to the first input; and a second operational amplifier configured to receive as input the second DVI communication data signal and to receive a second feedback signal from the reactive load and generate the second input signal applied to the second input.
6. The system of claim 4 , wherein the differential pair comprises first and second field effect transistors.
7. The system of claim 4 , wherein: the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.
8. The system of claim 3 , wherein the DDC extension circuit comprises: a voltage clamp connected to the receive end of the transmission line and operable to clamp a reflection signal caused by the DDC communication signals received at the receive end of the transmission line; and a current booster circuit connected to the receive end of the transmission line and operable to provide the boost current at the receive end of the transmission line when the DDC communication signal exceeds a first reference value and to eliminate the boost current from the receive end of the transmission line when the DDC communication signal exceeds a second reference value.
9. The system of claim 8 , wherein the voltage clamp comprises: a first comparator configured to receive as input the DDC communication signal and a first reference potential and to output a switch signal; and a first switch configured to receive the switch signal and to couple the receive end of the transmission line to a second reference potential when the DDC communication signal is less than the first reference potential.
10. The system of claim 9 , wherein the first and second reference potentials are a ground potential.
11. The system of claim 8 , wherein the current booster circuit comprises: a boost current circuit connected to the receive end of the transmission line, the boost current circuit operable to provide the boost current during an activated state; and a detector circuit operable to monitor the DDC communication signal on the receive end of the transmission line and to activate the boost current circuit when the DDC communication signal exceeds the first reference value and to deactivate the boost current circuit when the DDC communication signal exceeds the second reference value.
12. The system of claim 11 , wherein the detector circuit comprises: a level detector operable to output a first data signal when the DDC communication signal is less than the first reference value, and to output a second data signal when the DDC communication signal is greater than the first reference value and less than the second reference value, and to output a third data signal when the DDC communication signal is greater than the second reference value; and a latch circuit operable to receive the output data signals of the level detector and in response to selectively activate and deactivate the boost current circuit.
13. The system of claim 12 , wherein: the first reference value is a first reference voltage greater than a logic 0 voltage signal; and the second reference value is a second reference voltage greater than the first reference voltage.
14. The system of claim 11 , wherein the detector circuit comprises: a first comparator configured to receive as input the DDC communication signal and the first reference value and output a first comparator signal; a second comparator configured to receive as input the DDC communication signal and the second reference value and output a second comparator signal; and a latch configured to receive as input the first and second comparator signals and output a latch signal.
15. The system of claim 3 , wherein the DDC extension circuit comprises: a current booster circuit connected to the receive end of the transmission line, the current booster circuit operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and to eliminate the boost current at the end of the positive transition in the DDC communication signal and prevent injection of the boost current at the receive end of the transmission line during a negative transition in the DDC communication signal.
16. The system of claim 15 , wherein the current booster circuit is adapted to inject the boost current at the receive end of the transmission line when the DDC communication signal exceeds a first reference value and eliminate the boost current from the receive end of the transmission line when the DDC communication signal exceeds a second reference value, and to prevent injection of the boost current at the receive end of the transmission line when the DDC communication signal falls below the second and first reference values.
17. The system of claim 1 , wherein the open-loop equalizer is connected to a transmit end of the transmission line.
18. The system of claim 1 , wherein the open-loop equalizer is connected to the receive end of a transmission line.
19. The system of claim 1 , wherein the transmission line is a bus line.
20. The system of claim 1 , wherein the transmission line is a cable external to a computer device.
21. The system of claim 3 , wherein the DDC extension circuit is coupled to a bi-directional communication line in the transmission line.
22. A method for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line, comprising: providing feedback loops at the inputs to a differential pair, the feedback loops independent of output signals generated by the differential pair; providing as input to the feedback ioop the DVI communication data signals at the received end of the transmission line; generating first and second differential input signals from the DVI communication data signals and the feedback loop; monitoring the DDC communication signal at the receive end of the transmission line; and injecting a boost current at the receive end of the transmission line during a portion of the positive transition in the DDC communication signal; wherein the step of monitoring the DDC communication signal at a receive end of the transmission line comprises: generating an injection activation signal when the DDC communication signal exceeds a first reference value; and eliminating the injection activation signal when the DDC communication signal exceeds a second reference value; wherein the presence of the injection activation signal causes injection of the boost current at the receive end of the transmission line the step of monitoring the DDC communication signal at a receive end of the transmission line further comprising: generating a first output by a first comparator having a first input and a second input, the second input coupled to the receive end of the transmission line, the first output being high when the second input exceeds the first input and the first output being low when the second input does not exceed the first input; generating a second output by a second comparator having a third input and a fourth input, the fourth input coupled to the receive end of the transmission line, the second output being high when the fourth input exceeds the third input, and the second output being low when the fourth input does not exceed the third input; receiving the first output by a latch as a reset input and receiving the second output by the latch as a set input; receiving the output of the latch by a nand gate and receiving the inverted second output by the nand gate; and injecting the boost current when the output of the nand gate is high.
23. The method of claim 22 , wherein the step of providing feedback loops at the inputs to a differential pair comprise the step of providing unity gain feedback loops.
24. The method of claim 23 , wherein the step of providing feedback loops at the inputs to a differential pair comprise the step of generating a feedback signal from a reactive load connected to the differential pair.
25. The method of claim 23 , further comprising clamping a reflection signal caused by the DDC communication signal received at the receive end of the transmission line.
26. The method of claim 23 , further comprising the step compensating the DVI communication data signals for signal attenuation caused by ESD protection circuitry.
27. A system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line, comprising: means for providing feedback loops at the inputs to a differential pair, the feedback loops independent of output signals generated by the differential pair; means for providing as input to the feedback loop the DVI communication data signals at the received end of the transmission line; means for generating first and second differential input signals from the DVI communication data signals and the feedback loop; means for monitoring the DDC communication signal at the receive end of the transmission line; and means for injecting a boost current at the receive end of the transmission line during a portion of the positive transition in the DDC communication signal wherein the means for monitoring the DDC communication signal at the receive end of the transmission line comprises: means for generating an injection activation signal when the DDC communication signal exceeds a first reference value; and means for eliminating the injection activation signal when the DDC communication signal exceeds a second reference value; wherein the presence of the injection activation signal causes injection of the boost current at the receive end of the transmission line, the open-loop equalizer circuit providing a frequency dependent gain that is at or about the inverse of a frequency dependent attenuation caused by the transmission line, the DVI communication data signal being proportionally equalized, and if the open-loop equalizer provides a frequency dependent gain that is greater than the inverse of a frequency dependent attenuation caused by the transmission line, then the DVI communication data signal being proportionately equalized.
28. The system of claim 27 , wherein the means for providing feedback loops at the inputs to a differential pair are adapted for providing unity gain feedback loops.
29. The system of claim 28 , wherein the means for providing feedback loops at the inputs to a differential pair are adapted for generating a feedback signal from a reactive load connected to the differential pair.
30. The system of claim 27 , further comprising means for clamping a reflection signal caused by the DDC communication signal received at the receive end of the transmission line.
31. The system of claim 27 , further comprising means for compensating the DVI communication data signals for signal attenuation caused by the ESD protection circuitry before transmission over the transmission line.
Unknown
June 12, 2007
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