Round Robin Selection Logic Improves Area Efficiency and Circuit Speed

1. A method for round robin selection, comprising: providing an apparatus, comprising: a plurality of units each coupled to receive a different one of a plurality of request signals, an input signal, and a grant signal, wherein each unit produces a pointer signal; wherein the units are grouped to form a plurality of banks such that each bank includes at least two of the units; wherein each of the banks comprises a break loop pointer unit; wherein within each bank the units and the break loop pointer unit are connected in series such that the break loop pointer unit is coupled to receive a pointer signal produced by one of the units, and another one of the units is coupled to receive an output signal produced by the break loop pointer unit as the input signal; wherein the output signal produced by a break loop pointer unit is indicative of an active request signal received by one of the units within the bank including the break loop pointer unit; initializing one of the banks by setting the output signal produced by the break loop pointer unit of the bank to active, setting all of the request signals received by the units of the bank to inactive, and setting all of the pointer signals produced by the units of the bank to inactive; determining if a request signal received by one of the units of the bank is active; in the event a request signal received by one of the units of the bank is active: setting the output signal produced by the break loop pointer unit of the bank to inactive; setting the pointer signal produced by the unit receiving the active request signal to active; waiting for the grant signal received by the unit receiving the active request signal to become active; and inactivating the active request signal and the active pointer signal.

2. An apparatus for arbitrating among a plurality of requestors each producing a request signal, the apparatus comprising: a plurality of requestor latches each coupled to receive a different one of the request signals and a grant signal, and configured to produce a latch output signal dependent upon the request signal and the grant signal; a plurality of pointing logic sequence units each corresponding to a different one of the requester latches, wherein each of the pointing logic sequence units is coupled to receive an input signal and the latch output signal produced by the corresponding requester latch, and is configured to produce an output signal dependent upon the input signal and the latch output signal; wherein the requestor latches and the corresponding pointing logic sequence units are grouped to form a plurality of banks such that each bank includes at least two of the requester latches and the corresponding pointing logic sequence units; wherein each of the banks comprises a break loop pointer unit; wherein within each bank, the pointing logic sequence units and the break loop pointer unit are connected in series such that the break loop pointer unit is coupled to receive an output signal produced by one of the pointing logic sequence units, and another one of the pointing logic sequence units is coupled to receive an output signal produced by the break loop pointer unit as the input signal; and wherein the output signal produced by a break loop pointer unit is indicative of an asserted request signal received by a requestor latch within the bank including the break loop pointer unit.

3. The apparatus as recited in claim 2 , wherein each of the requester latches comprises a latch.

4. The apparatus as recited in claim 3 , wherein each of the requestor latches comprises an AND gate receiving the request signal and an output signal produced by the latch.

5. The apparatus as recited in claim 2 , wherein each of the pointing logic sequence units comprises a latch.

6. The apparatus as recited in claim 2 , wherein each of the pointing logic sequence units is configured to produce a first output signal and a second output signal dependent upon the input signal and the latch output signal, and wherein each of the requester latches is coupled to receive the second output signal and is configured to produce the latch output signal dependent upon the second output signal.

7. The apparatus as recited in claim 6 , wherein each of the requestor latches comprises a latch, a first AND gate receiving the request signal and an output signal produced by the latch, and a second AND gate receiving the grant signal and the second output signal.

8. The apparatus as recited in claim 2 , wherein each of the pointing logic sequence units comprises an AND-OR-INVERT sequence unit and a pointing latch sequence unit.

9. The apparatus as recited in claim 8 , wherein each AND-OR-INVERT sequence unit comprises an AND gate and a NOR gate, wherein the AND gate is coupled to receive the input signal received by the pointing logic sequence unit including the AND-OR-INVERT sequence unit, and wherein the NOR gate is coupled to receive an output signal produced by the AND gate and the latch output signal, and is configured to produce the output signal of the pointing logic sequence unit including the AND-OR-INVERT sequence unit.

10. The apparatus as recited in claim 8 , wherein each pointing latch sequence unit comprises a latch.

11. The apparatus as recited in claim 10 , wherein within each pointing logic sequence unit, the AND-OR-INVERT sequence unit comprises an AND gate and a NOR gate, wherein the AND gate is coupled to receive the input signal received by the pointing logic sequence unit and an output signal produced by the latch of the pointing latch sequence unit, and wherein the NOR gate is coupled to receive an output signal produced by the AND gate and the latch output signal, and is configured to produce the output signal of the pointing logic sequence unit.