I/O and Memory Bus System for Dfps and Units with Two-Or Multi-Dimensional Programmable Cell Architectures

1. An arrangement, comprising: a processor including a plurality of cells configurable with regard to at least one of function and interconnections; at least one memory, an address arrangement configured to address the at least one memory; and an internal global bus system communicatively coupled to the address arrangement, the plurality of cells being connectable via the internal global bus system; wherein the address arrangement is further configured to indicate an end of a data transfer via a signal on a bus.

2. The arrangement according to claim 1 , wherein the address arrangement is an address generator.