Enable/Disable Claiming of a Dma Request Interrupt

1. A machine-readable storage medium comprising a plurality of instructions that, in response to being executed by a computing device, results in the computing device defining an interrupt as a DMA request interrupt, causing a device to generate the interrupt each time the device is ready for a transfer of a data block, storing a DMA structure in a memory that defines a DMA transfer between the memory and the device in response to the first generation of the interrupt, enabling claiming of the interrupt by a chipset to prevent delivery of further generations of the interrupt to a processor of the computing device, and configuring the chipset to transfer a data block per the DMA structure each time the device generates the interrupt.

2. The machine-readable storage medium of claim 1 wherein the plurality of instructions further result in the computing device configuring the chipset to deliver at least one of the claimed interrupts to the processor after the DMA transfer.

3. The machine-readable storage medium of claim 1 wherein the plurality of instructions further result in the computing device defining the interrupt as a DMA request interrupt based upon a interrupt number associated with the interrupt.

4. The machine-readable storage medium of claim 1 wherein the plurality of instructions further result in the computing device defining the interrupt as a DMA request interrupt based upon a interrupt vector associated with the interrupt.

5. The machine-readable storage medium of claim 1 wherein the plurality of instructions further result in the computing device disabling claiming of the interrupt by the chipset after completing the DMA transfer defined by the DMA structure.

6. A method comprising: defining an interrupt as a DMA request interrupt, causing a device to generate the interrupt each time the device is ready for a transfer of a data block, storing a DMA structure in a memory that defines a DMA transfer between the memory and the device in response to the first generation of the interrupt, enabling claiming of the interrupt by a chipset to prevent delivery of further generations of the interrupt to a processor of the computing device, and configuring the chipset to transfer a data block per the DMA structure each time the device generates the interrupt.

7. The method of claim 6 , further comprising: configuring the chipset to deliver at least one of the claimed interrupts to the processor after the DMA transfer.

8. The method of claim 6 , further comprising: defining the interrupt as a DMA request interrupt based upon a interrupt number associated with the interrupt.

9. The method of claim 6 , further comprising: defining the interrupt as a DMA request interrupt based upon a interrupt vector associated with the interrupt.

10. The method of claim 6 , further comprising: disabling claiming of the interrupt by the chipset after completing the DMA transfer defined by the DMA structure.