Minimum Delta Generator for Program Binaries

1. A computer-implemented method for facilitating matching of blocks between a first control flow graph (CFG) representation of a portion of a first set of executable instructions and a second CFG representation of a portion of a second set of executable instructions, wherein the instructions are embodied on one or more computer-readable media, the method comprising: computing register flows for each block by analyzing a def-use chain and a use-def chain; for each block, assigning def-identifiers to definitions (“def”s) of each register; for each block, associating a use of a register in a block with the def identifier of all defs of that register that reach the use; matching blocks between the first and second CFG representations based upon the def-identifiers and use-identifiers, whereby facilitating matching of blocks between the first control flow graph (CFG) representation of the portion of the first set of executable instructions and the second CFG reoresentation of the portion of the second set of executable instructions.

2. A computer-readable storage medium having computer-executable instructions that, when executed by a computer, performs the method as recited in claim 1 .

3. One or more computer-readable storage media having computer-executable instructions that, when executed by a computer, performs a method comprising matching blocks between a first control flow graph (CFG) representation of a portion of a first set of executable instructions and a second CFG representation of a portion of a second set of executable instructions, wherein the matching comprises determining whether blocks match except for nominal differences; computing register flows for each block by analyzing a def-use chain and a use-def chain, wherein a use-def chain is a list comprising a register use and a plurality of definitions (“defs”) of that register that reach that register use and a def-use chain is a list comprising a register def and each use of the register, reached by the register def; for each block, assigning def-identifiers to definitions (“def”s) of each register; for each block, associating a use of a register in a block with the def identifier of all defs of that register that reach this use; matching blocks between the first and second CFG reoresentations based upon the def-identifiers and use-identifiers, whereby facilitating matching of blocks between the first control flow graph (CFG) representation of the portion of the first set of executable instructions ancLthe second CFG representation of the portion of the second set of executable instructions.

4. A system for facilitating matching of blocks between a first control flow graph (CFG) representation of a portion of a first set of executable instructions and a second CFG representation of a portion of a second set of executable instructions, the system comprising: a means for computing register flows for each block by analyzing a def-use chain and a use-def chain; for each block, a means for assigning def-identifiers to definitions (“def”s) of each register; for each block, a means for associating a use of a register in a block with the def identifier of all defs of that register that reach the use; a means for matching blocks between the first and second CFG representations based upon the def-identifiers and use-identifiers, whereby facilitating matching of blocks between the first control flow graph (CFG) representation of the portion of the first set of executable instructions and the second CFG representation of the nortion of the second set of executable instructions.