Memory Circuit Comprising an Error Correcting Code

1. A memory circuit having an error correcting system comprising: an input address bus; an input data bus; an output data bus, and a memory, electrically coupled to the input address bus, the input data bus, and the output data bus, and having an address bus, a data bus, and an error correcting circuit comprising an encoder, wherein the memory comprises: a first register connected to the input address bus for successively storing addresses corresponding to memory write operations only; a second register connected to the input data bus for storing data transmitted to the encoder; and means for introducing a one-cycle shift into memory write, without modifying memory read.

2. The memory circuit according to claim 1 , comprising: a single port memory having an address bus, an input data bus, and an output data bus; a multiplexer having a first input and a second input, an output and a control electrode, the first input being connected to the input address bus of the memory circuit, the second input being connected to the output of the first register, the output being connected to the address bus of the single port memory and the control electrode receiving a write enable signal.

3. The memory circuit according to claim 2 , comprising: a comparator having two inputs connected to the input address bus of the memory circuit and to an output of the first register, respectively; a second multiplexer having a first input, a second input, an output, and a control electrode; the first input of the second multiplexer being connected to the output of the second register; the second input of the second multiplexer being connected to the output data bus of the single port memory; the output of the second multiplexer being connected to the output data bus of the memory circuit; and the control electrode receiving a control signal provided by the comparator.

4. The memory circuit according to claim 1 , comprising: a first single port memory for storing data and a second double port memory for storing error correcting codes, recording of the error correcting codes being delayed until a next write cycle.

5. The memory circuit according to claim 4 , comprising: an ECC decoder circuit for detecting an error in the first memory; and a set of multiplexers for placing a write operation in the first memory within the next cycle, in response to the ECC decoder circuit detecting an error.

6. The memory circuit according to claim 1 , comprising: a first single port memory for storing data; and a second single port memory for storing error correcting codes, recording of the error correcting codes being delayed until the next write cycle.

7. The memory circuit according to claim 6 , comprising: an ECC decoder circuit for detecting an error in the first single port memory; and a set of multiplexers for placing a write operation in the first single port memory within the next cycle, in response to the detection of an error by the ECC decoder circuit.

8. The memory circuit according to claim 1 , comprising: a synchronous static memory.

9. A memory circuit according to claim 1 , comprising: at least one of a SEC-DED-type and a DED-TED-type code correcting system.

10. An integrated circuit comprising: a circuit supporting substrate; and a memory circuit disposed on the circuit supporting substrate, the memory circuit comprising: an input address bus; an input data bus; an output data bus, and a memory, electrically coupled to the input address bus, the input data bus, and the output data bus, and having an address bus, a data bus, and an error correcting circuit comprising an encoder, wherein the memory comprises: a first register connected to the input address bus of the memory circuit for successively storing addresses corresponding to memory write operations only; a second register connected to the input data bus of the memory circuit for storing data transmitted to the encoder; and means for introducing a one-cycle shift into memory write, without modifying memory read.

11. The integrated circuit according to claim 10 , comprising: a single port memory having an address bus, an input data bus, and an output data bus; and a multiplexer having a first input and a second input, an output and a control electrode, the first input being connected to the input address bus of the memory circuit, the second input being connected to the output of the first register, the output being connected to the address bus of the single port memory and the control electrode receiving a write enable signal.

12. The integrated circuit according to claim 11 , comprising: a comparator having two inputs connected to the input address bus of the memory circuit and to an output of the first register, respectively; a second multiplexer having a first input, a second input, an output, and a control electrode; the first input of the second multiplexer being connected to the output of the second register; the second input of the second multiplexer being connected to the output data bus of the single port memory; the output of the second multiplexer being connected to the output data bus of the memory circuit; and the control electrode receiving a control signal provided by the comparator.

13. The integrated circuit according to claim 10 , comprising: a first single port memory for storing data; and a second double port memory for storing error correcting codes, recording of the error correcting codes being delayed until a next write cycle.

14. The integrated circuit according to claim 13 , comprising: an ECC decoder circuit for detecting an error in the first memory; and a set of multiplexers for placing a write operation in the first memory within the next cycle, in response to the ECC decoder circuit detecting an error.

15. The integrated circuit according to claim 10 , comprising: a first single port memory for storing data; and a second single port memory for storing error correcting codes, recording of the error correcting codes being delayed until the next write cycle.

16. The integrated circuit according to claim 15 , comprising: an ECC decoder circuit for detecting an error in the first single port memory; and a set of multiplexers for placing a write operation in the first single port memory within the next cycle, in response to the detection of an error by the ECC decoder circuit.

17. The integrated circuit according to claim 10 , comprising: a synchronous static memory.

18. The integrated circuit according to claim 10 , comprising: at least one of a SEC-DED-type and a DED-TED-type code correcting system.

19. A computer system comprising: at least one processor; and at least one integrated circuit communicatively coupled with the at least one processor, each of the at least one integrated circuit comprising: a circuit supporting substrate; and a memory circuit disposed on the circuit supporting substrate, the memory circuit comprising: an input address bus; an input data bus; an output data bus, and a memory, electrically coupled to the input address bus, the input data bus, and the output data bus, and having an address bus, a data bus, and an error correcting circuit comprising an encoder, wherein the memory comprises: a first register connected to the input address bus of the memory circuit for successively storing addresses corresponding to memory write operations only; a second register connected to the input data bus of the memory circuit for storing data transmitted to the encoder; and means for introducing a one-cycle shift into memory write, without modifying memory read.

20. A memory circuit having an error correcting system comprising: a first input address bus; a first input data bus; a first output data bus, and a memory, electrically coupled to said first input address bus, said first input data bus, and said first output data bus, and having a second input address bus, a second input data bus, a second output data bus, and an error correcting circuit comprising an encoder, wherein the memory comprises: a first register connected to said first input address bus for successively storing addresses corresponding to memory write operations only; a first multiplexor having a first input connected to said first input address bus and a second input connected to the output of said first address register, said first multiplexor being controlled by a Write Enable signal and having an output connected to said second address bus; a second register connected to said first input data bus for storing data transmitted to the encoder; a comparator having a first input connected to said first input address bus and a second input connected to the output of said first register, said comparator generating a control signal when the address stored within said first register is identical to the address currently present on said first address bus; and p 2 a second multiplexor having a first input connected to said second output data bus and a second input connected to the output of said second register and an output which is connected to said first output data bus, said second multiplexor being controlled by said control signal generated by said comparator; whereby said first and second registers, said first and second multiplexor and said encoder are controlled so as to differ the storage of every data to be written within said memory until the next Write operation by means of a temporary storage of said address and data in said first and said second register while the error correcting code is computed by said encoder.

21. An integrated circuit comprising: a circuit supporting substrate; and a memory circuit disposed on the circuit supporting substrate, the memory circuit comprising: a first input address bus; a first input data bus; a first output data bus, and a memory, electrically coupled to said first input address bus, said first input data bus, and said first output data bus, and having a second input address bus, a second input data bus, a second output data bus, and an error correcting circuit comprising an encoder, wherein the memory comprises: a first register connected to said first input address bus for successively storing addresses corresponding to memory write operations only; a first multiplexor having a first input connected to said first input address bus and a second input connected to the output of said first address register, said first multiplexor being controlled by a Write Enable signal and having an output connected to said second address bus; a second register connected to said first input data bus for storing data transmitted to the encoder; a comparator having a first input connected to said first input address bus and a second input connected to the output of said first register, said comparator generating a control signal when the address stored within said first register is identical to the address currently present on said first address bus; and a second multiplexor having a first input connected to said second output data bus and a second input connected to the output of said second register and an output which is connected to said first output data bus, said second multiplexor being controlled by said control signal generated by said comparator; whereby said first and second registers, said first and second multiplexor and said encoder are controlled so as to differ the storage of every data to be written within said memory until the next Write operation by means of a temporary storage of said address and data in said first and said second register while the error correcting code is computed by said encoder.