Method for Designing an Initiatior in an Integrated Circuit

1. An integrated circuit with an arbiter comprising: a plurality of initiators and targets; a communication interconnect between the initiators and the targets; and an arbiter provided between the initiators and the communication interconnect comprising: an input for receiving a plurality of packet-format requests from a plurality of the initiators; arbitration logic for arbitrating between said requests in accordance with an arbitration method, wherein the arbitration method specifies whether each of the initiators or the interconnect is responsible for ordering packet-format responses from the targets; a store for storing information defining the priority of said initiators, wherein said arbitration logic is arranged to update said store after arbitration to define the priority of said sources for a subsequent arbitration.

2. An integrated circuit as claimed in claim 1 , wherein the store comprises a table in which the position of the initiator in the table determines the priority of the initiator.

3. An integrated circuit as claimed in claim 1 , comprising packet control logic for maintaining the ordering of packets containing the requests.

4. The integrated circuit of claim 1 , further comprising: a queue for storing a predetermined maximum number of outstanding ones of the requests, said queue comprising: a store for storing the outstanding requests, a location being provided for each of the maximum number of outstanding requests; logic for determining if each of said locations contains an outstanding request and if so to provide a signal indicating that the queue is full.

5. The integrated circuit of claim 1 , wherein the arbitration logic further determines whether a delay is to be provided after arbitration has been performed.

6. The integrated circuit of claim 5 , wherein at least a portion of the initiators comprise a delay stage for performing the delay after the arbitration.

7. The integrated circuit of claim 4 , wherein the queue is positioned between the initiator and the interconnect.

8. An integrated circuit with an arbiter comprising: a plurality of initiators and targets; a communication interconnect between the initiators and the targets; and an arbiter provided between the initiators and the communication interconnect comprising: an input for receiving a plurality of packet-format requests from a plurality of the initiators; arbitration logic for arbitrating between said requests in accordance with an arbitration method, wherein the arbitration method specifies whether each of the initiators is responsible for ensuring time-based ordering of packet is handled and whether a delay is provided after the arbitrating.

9. The integrated circuit of claim 8 , wherein the arbiter further comprises a store for storing information defining the priority of said initiators, and wherein said arbitration logic is arranged to update said store after arbitration to define the priority of said sources for a subsequent arbitration.

10. The integrated circuit of claim 8 , further comprising: a queue for storing a predetermined maximum number of outstanding ones of the requests, said queue comprising: a store for storing the outstanding requests, a location being provided for each of the maximum number of outstanding requests; logic for determining if each of said locations contains an outstanding request and if so to provide a signal indicating that the queue is full.

11. The integrated circuit of claim 8 , wherein at least a portion of the initiators comprise a delay stage for performing the delay after the arbitration.

12. The integrated circuit of claim 10 , wherein the queue is positioned between the initiator and the interconnect.

13. An integrated circuit with an arbiter comprising: a plurality of initiators and targets; a communication interconnect between the initiators and the targets; a request arbiter provided between the initiators and the communication interconnect comprising: an input for receiving a plurality of packet-format requests from a plurality of the initiators; and request arbitration logic for arbitrating between said requests in accordance with an arbitration method, wherein the arbitration method specifies whether each of the initiators is responsible for ensuring time-based ordering of packet is handled and whether a delay is provided after the arbitrating; and a request provided between the targets and the communication interconnect comprising: an input for receiving a plurality of packet-format responses to the requests from a plurality of the targets; target arbitration logic for arbitrating between said responses in accordance with a target arbitration method.

14. The integrated circuit of claim 13 , wherein the target arbitration method specifies whether each of the targets is responsible for ensuring time-based ordering of packet is handled.

15. The integrated circuit of claim 13 , wherein the target arbitration method specifies whether a delay is provided after the arbitrating by the request arbiter.

16. The integrated circuit of claim 13 , wherein the target arbitration method differs from the request arbitration method.