Method and Data Processor with Reduced Stalling Due to Operand Dependencies

1. For use in a data processor having a pipelined execution unit, a method comprising the steps of: determining whether a first instruction is one of a class of instructions consisting of: an add instruction between a first operand stored in a operand register and a second operand having a value of zero, wherein a result of said add instruction is to be stored in a destination register; and a multiply instruction between said first operand stored in said operand register and a third operand having a value of one, wherein a result of said multiply instruction is to be stored in said destination register; receiving a second instruction that references said destination register before a completion of execution of said first instruction; and executing said second instruction using said operand register in place of said destination register in response to determining the first instruction is one of the class of instructions.

2. The method of claim 1 further comprising the step of associating said operand register with an operand register identifier of said second instruction that was previously associated with said destination register before said step of executing.

3. The method of claim 2 wherein said step of associating comprises the steps of: storing in a match field of a redirect register a register identifier of said destination register; and storing in a substitute field of said redirect register a register identifier of said operand register.

4. The method of claim 3 wherein said step of executing comprises the steps of: comparing an operand register identifier of said second instruction with the contents of said match field to provide a match signal; substituting the contents of said substitute field for said operand register identifier of said operand register to provide a new register identifier in response to the contents of said match field; and executing said second instruction using said new register identifier.

5. For use in a data processor having a pipelined execution unit, a method comprising the steps of: determining whether a first instruction is one of a class of instructions consisting of: an add instruction between a first operand stored in an operand register and a second operand having a value of zero, wherein a result of said add instruction is to be stored in a destination register; and a multiply instruction between said first operand stored in said operand register and a third operand having a value of one, wherein a result of said multiply instruction is to be stored in said destination register; if said first instruction is one of said class of instructions, storing a destination register identifier associated with said destination register in a match field of a redirect register, an operand register identifier associated with said operand register in a substitute field of said redirect register, and a valid bit in a valid field of said redirect register; receiving a second instruction before a completion of execution of said first instruction; comparing a first operand register identifier of said second instruction with the contents of said match field when said valid bit is in a predetermined logic state; and executing said second instruction using the contents of a register indicated by said substitute field without stalling said second instruction in the pipelined execution unit if said first operand register identifier matches the contents of said match field.

6. The method of claim 5 further comprising the steps of: if said first instruction is one of said class of instructions, further storing a sign bit of said first instruction in a sign field of said redirect register; and selectively changing a sign bit of a result of execution of said second instruction in response to said sign bit of said redirect register.

7. The method of claim 5 further comprising the steps of: comparing a second operand register identifier of said second instruction with the contents of said match field when said valid bit is in said predetermined logic state; and executing said second instruction using the contents of said register indicated by said substitute field without stalling said second instruction in the pipelined execution unit if either said first operand register identifier or said second operand register identifier matches the contents of said match field.

8. The method of claim 5 wherein said step of determining comprises the steps of: detecting that a fraction field of said third operand has a value of zero; and detecting that an exponent field of said third operand has a maximum value.

9. The method of claim 5 wherein said step of executing comprises the steps of: detecting a normal pipeline dependency if said first operand register identifier of said second instruction matches a destination register identifier of any one of a plurality of previous instructions including said first instruction; and performing said step of executing without stalling by overriding said normal pipeline dependency if said first operand register identifier of said second instruction matches the contents of said match field.

10. A data processor comprising: an issue logic circuit having an output for providing first and second instructions in sequence, each instruction having at least an opcode, a first operand register identifier for a first operand, and a destination register identifier for a destination register; a register file having a read port including a read address input and a read data output, and a write port; a pipelined execution unit having a first input coupled to said output of said issue logic circuit, a second input coupled to said read data output of said register file, and an output coupled to said write port of said register file; and a redirect logic circuit having a first input coupled to said output of said issue logic circuit, a second input coupled to said read data output of said register file, and an output coupled to said read address input of said register file for selectively substituting said first operand register identifier of said first instruction for said first operand register identifier of said second instruction, wherein said redirect logic circuit substitutes said first operand register identifier of said first instruction for said first operand register identifier of said second instruction if it determines that as a result of execution of said first instruction said destination register of said first instruction will contain the contents of said first operand register of said first instruction and wherein said redirect logic circuit further comprises: a redirect detect logic circuit having an output terminal: a first redirect register coupled to said output of said issue logic circuit and associated with a stage of said pipelined execution unit, having at least a valid field coupled to said output terminal of said redirect detect logic circuit, a match field for receiving said destination register identifier, and a substitute field for receiving a selected one of said first operand register identifier and a second operand register identifier; a first comparator having a first input terminal for receiving said first operand register identifier of said second instruction, a second input terminal coupled to said match field of said first redirect register, a control input terminal coupled to said valid field of said first redirect register, and an output terminal: and a first multiplexer having a first input terminal for receiving said first operand register identifier, a second input terminal coupled to said substitute field of said first redirect register, a control input terminal coupled to said output terminal of said first comparator, and an output terminal for providing a new register identifier for said first operand of said second instruction.

11. The data processor of claim 10 wherein said redirect logic circuit further comprises: a second redirect register having an input terminal coupled to an output terminal of said first redirect register, and having a valid field, a match field, and a substitute field coupled to corresponding fields in said first redirect register; and a second comparator having a first input terminal for receiving said first operand register identifier of said second instruction, a second input terminal coupled to said match field of said second redirect register, a control input terminal coupled to said valid field of said second redirect register, and an output terminal; wherein said first multiplexer further has a third input terminal coupled to said substitute field of said second redirect register, and a second control input terminal coupled to said output terminal of said second comparator, wherein said first multiplexer provides said new register identifier for said first operand of said second instruction to said output terminal in dependence on signals at said output terminals of both said first and second comparators.

12. The data processor of claim 10 wherein said redirect logic circuit further comprises: a third comparator having a first input terminal for receiving said second operand register identifier of said second instruction, a second input terminal coupled to said match field of said first redirect register, a control input terminal coupled to said valid field of said first redirect register, and an output terminal; and a second multiplexer having a first input terminal for receiving said second operand register identifier, a second input terminal coupled to said substitute field of said first redirect register, a control input terminal coupled to said output terminal of said third comparator, and an output terminal for providing a new register identifier for said second operand of said second instruction.

13. The data processor of claim 12 wherein said redirect logic circuit further comprises: a second redirect register having an input terminal coupled to said output terminal of said first redirect register, and having a valid field, a match field, and a substitute field coupled to corresponding fields in said first redirect register; and a fourth comparator having a first input terminal for receiving said second operand register identifier of said second instruction, a second input terminal coupled to said match field of said second redirect register, a control input terminal coupled to said valid field of said second redirect register, and an output terminal; wherein said second multiplexer further has a third input terminal coupled to said substitute field of said second redirect register, and a second control input terminal coupled to said output terminal of said second comparator, wherein said second multiplexer provides said new register identifier for said second operand of said second instruction to said output terminal in dependence on signals at said output terminals of both said third and fourth comparators.

14. The data processor of claim 10 wherein a second input of said pipelined execution unit is coupled to said read data output of said register file through a bypass circuit, said output of said pipelined execution unit is coupled to said write port of said register file through said bypass circuit, and said second input of said redirect logic circuit is coupled to said read data output of said register file through said bypass circuit.

15. The data processor of claim 10 wherein said instruction further includes a second operand register identifier for a second operand.