Methods and Apparatus for Decoding and Displaying Different Resolution Video Signals

1. A video signal decoder module for processing video signals of different resolutions, said different resolutions including a first resolution and a second resolution, the first resolution being a higher resolution than said second resolution, the video signal decoder module comprising: a mode control circuit for controlling said decoder module to operate in one of a plurality of different modes of operation, said plurality of different modes of operation including a first mode of operation during which a particular data reduction operation is performed and a second mode of operation during which decoding is performed without performing said particular data reduction operation which is performed during said first mode of operation, said mode control circuit controlling said decoder to operate in said first data reduction mode of operation when processing video signals of the first resolution and operating in the second mode of operation when processing video signals of the second resolution; a controllable data reduction circuit for performing said particular data reduction operation when said mode control circuit indicates that operation in said first mode of operation but not when said mode control circuit indicates that operation is in said second mode of operation; and a memory for storing decoded video signals produced when operating in either of said first and second modes of operation.

2. The video signal decoder module of claim 1 , wherein said video signals are MPEG-2 compliant television signals.

3. The video signal decoder module of claim 2 , wherein said first resolution is a high definition resolution.

4. The video signal decoder module of claim 3 , wherein said second resolution is a Standard Definition resolution.

5. The video signal decoder module of claim 3 , wherein said second resolution is approximately an NTSC resolution.

6. The video signal decoder module of claim 1 , further comprising: an inverse discrete cosine circuit, coupled to said controllable data reduction circuit for performing an inverse discrete cosine decoding operation on video signals of said first resolution subsequent to said data reduction operation being performed.

7. The video signal decoder module of claim 6 , wherein said controllable data reduction circuit is a preparser for discarding at least some video signal data before processing by said inverse discrete cosine transform circuit.

8. The video signal decoder module of claim 7 , wherein said at least some video signal data which is discarded includes at least one DCT coefficient.

9. The video signal decoder module of claim 6 , further comprising: a controllable motion compensated prediction circuit supporting first and second modes of motion compensated prediction operations, said controllable motion compensated prediction module including an upsampler used during said first mode of operation to upsample reference frames from said memory to be used in making motion compensated predictions.

10. The video signal decoder module of claim 7 , further comprising: an output coupled for outputting decoded image data to a display device.

11. The video signal decoder module of claim 1 , further comprising: an output for outputting decoded image data to a display device.

12. The video signal decoder module of claim 1 , further comprising: an inverse discrete cosine circuit, coupled to said controllable data reduction circuit for performing an inverse discrete cosine decoding operation on video signals of said first resolution prior to said data reduction operation being performed.

13. The video signal decoder module of claim 12 , wherein said controllable data reduction circuit is a data reduction module for discarding at least some video signal data.

14. The video signal decoder module of claim 13 , wherein said data reduction module is a down sampling module.

15. The video signal decoder module of claim 13 , wherein said data reduction is performed before storage of video signal data in said memory.

16. The video signal decoder module of claim 13 , wherein said memory is a decoded frame store.

17. The video signal decoder module of claim 16 , further comprising: an output for outputting decoded image data to a display device.

18. The video signal decoder module of claim 1 , wherein said video signal decoder module is a television signal decoder and wherein said video signals are television signals.

19. A method of processing video signals of different resolutions, said different resolutions including a first resolution and a second resolution, the first resolution being a higher resolution than said second resolution, the method comprising: generating at least one mode control signal to control video signal processing operations as a function of the type of video signal being processed, said step of generating at least one mode control signal including generating a data reduction mode control signal to cause operation to be performed in accordance with a first data reduction mode of operation when processing signals of the first resolution and generating a second mode control signal when the signal to be processed is of the second resolution, the second mode control signal causing operation to be performed in accordance with a second processing mode of operation; performing a data reduction operation when a generated mode control signal indicates that operation is to be performed in said first mode of operation but not when said mode control circuit indicates that operation is to be performed in said second mode of operation; and storing decoded video signals in a memory produced when operating in either of said first and second modes of operation.

20. The method of claim 19 , wherein said video signals are MPEG-2 compliant television signals.

21. The method of claim 19 , wherein said first resolution is a high definition resolution.

22. The method of claim 21 , wherein said second resolution is a Standard Definition resolution.

23. The method of claim 21 , wherein said second resolution is approximately an NTSC resolution.

24. The method of claim 19 , further comprising: performing an inverse discrete cosine decoding operation on video signals of said first resolution subsequent to said data reduction operation being performed.

25. The method of claim 24 , wherein said controllable data reduction operation includes a preparsing operation which discards at least some video signal data before processing by said inverse discrete cosine transform circuit.

26. The method of claim 25 , wherein said at least some video signal data which is discarded includes at least one DCT coefficient.

27. The method of claim 24 , further comprising: performing a motion compensated prediction operation as a function of the generated mode control signal, said motion compensated prediction operation including an upsampling operation performed during said when the generated mode control signal indicates the data reduction mode of operation, said upsampling including upsampling at least one reference frame obtained from said memory and making a motion compensated prediction using the upsampled frame.

28. The method of claim 25 , further comprising: outputting decoded image data from said memory to a display device.

29. The method of claim 19 , further comprising: performing an inverse discrete cosine decoding operation on video signals of said first resolution prior to performing said data reduction operation.

30. The method of claim 29 , wherein said data reduction operation includes discarding at least some video signal data.

31. The method of claim 30 , wherein said data reduction operating includes downsampling.

32. The method of claim 30 , wherein said data reduction is performed on decoded video signal data, produced by performing said inverse discrete cosine decoding operation, prior to storing the decoded video signal data in said memory.

33. The method of claim 30 , wherein said memory is a decoded frame store.

34. The method of claim 33 , further comprising: outputting decoded image data to a display device.

35. A video signal processing apparatus for processing video signals of different resolutions, said different resolutions including at least a first resolution and a second resolution, the first resolution being a higher resolution than said second resolution, the processing apparatus comprising: a decoder module for performing at least one image decoding operation; a mode control module for generating a mode control signal, said mode control module controlling said mode control signal to indicate a first mode of operation when video signals of the first resolution are being processed and to indicate a second mode of operation when video signals of the second resolution are being processed; a controllable data reduction module coupled to said mode control module for performing a data reduction operation under control of the mode control signal used to indicate if video signal processing is to be performed in a first mode of operation or in a second mode of operation, said controllable data reduction module performing at least one data reduction operation when said first mode of operation is indicated by the mode control signal which is not performed when said second mode of operation is indicated by said mode control signal; and a memory for storing decoded image data produced when operating in at least one of said first and second modes of operation.

36. The apparatus of claim 35 , wherein said decoder module includes: an inverse discrete cosine circuit, coupled to said controllable data reduction module for performing an inverse discrete cosine decoding operation on video signals of said first resolution prior to processing by said data reduction module.

37. The apparatus of claim 36 , wherein said controllable data reduction module discards at least some video signal data.

38. The apparatus of claim 37 , wherein said data reduction module includes a down sampling module.

39. The apparatus of claim 36 , wherein said memory is a decoded frame store.

40. The apparatus of claim 39 , further comprising: an output for outputting decoded image data to a display device.