Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: receiving a first process, comprising successive computational phases, to be executed by a processor in a data processing system; assigning the first process to run on a first processor; determining a first prefetch status for the first process at each of successive times when the first process is running, wherein each determined first prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the first process; setting a first hardware prefetch state on the first processor based on each determined first prefetch status to correspondingly enable or disable said hardware prefetch; receiving a second process, comprising successive computational phases, to be executed by a processor in the data processing system; assigning the second process to run on a second processor; determining a second prefetch status for the second process at each of successive times when the second process is running, wherein each determined second prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the second process; and setting a second hardware prefetch state on the second processor based on each determined second prefetch status, to correspondingly enable or disable said hardware prefetch.
2. The method of claim 1 , wherein a hardware prefetch of each processor of said data processing system is individually enabled or disabled, selectively.
3. The method of claim 1 , wherein determining a prefetch status includes examining a prefetch status indicator in a given process.
4. The method of claim 3 , wherein the prefetch status indicator is a bit in a machine status word.
5. The method of claim 1 , wherein setting a hardware prefetch state on a given processor includes writing a machine status word to a machine status register in the given processor.
6. The method of claim 1 , further comprising: context-switching the second process to run on the first processor.
7. The method of claim 5 , wherein the the machine status word is included in a context block of the given process.
8. The method of claim 1 , wherein hardware prefetch is enabled for the first processor and disabled for the second processor.
9. The method of claim 1 , wherein determining a prefetch status for a given process includes receiving a system call from the given process.
10. The method of claim 1 , wherein determining a prefetch status for a given process and setting a hardware prefetch state on a given processor are performed by a performance monitor in the given processor.
11. The method of claim 10 , wherein the performance monitor determines performance statistics for the given process and determines whether hardware prefetch should be enabled for the given process based on the performance statistics.
12. A data processing system, comprising: at least one processor; and an operating system running on the at least one processor, wherein the operating system receives a first process, assigns the first process to run on a first processor, determines a first prefetch status for the first process at each of successive times when the first process is running, wherein each determined first prefetch status indicates whether hardware prefetch should be enabled or disabled for the next following computational phase of the first process, sets a first hardware prefetch state on the first processor based on each determined first prefetch status, to correspondingly enable or disable said hardware prefetch; receives a second process, assigns the second process to run on a second processor, determines a second prefetch status for the second process at each of successive times when the second process is running, wherein each determined second prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the second process, and sets a second hardware prefetch state on the second processor based on each determined second prefetch status, to correspondingly enable or disable said hardware prefetch.
13. The data processing system of claim 12 , wherein a hardware prefetch of each processor of said data processing system is individually enabled or disabled, selectively.
14. The data processing system of claim 12 , wherein the operating system determines the prefetch status by examining a prefetch status indicator in a given process.
15. The data processing system of claim 14 , wherein the prefetch status indicator is a bit in a machine status word.
16. The data processing system of claim 15 , wherein the operating system sets a hardware prefetch state on a given processor by writing the machine status word to a machine status register in the given processor.
17. The data processing system of claim 12 , wherein the first prefetch status is enabled and the second prefetch status is disabled.
18. The data processing system of claim 15 , wherein the machine status word is included in a context block of the given process.
19. The data processing system of claim 12 , wherein hardware prefetch is enabled for the first processor and disabled for the second processor.
20. The data processing system of claim 12 , wherein the operating system determines a prefetch status for a given process by receiving a system call from the given process.
21. A computer program product, embedded in a computer readable recordable media and executable by a data processing system, comprising: instructions for receiving a first process, comprising successive computational phases, to be executed by a processor in a data processing system; instructions for assigning the first process to run on a first processor; instructions for determining a first prefetch status for the first process at each of successive times when the first process is running, wherein each determined first prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the first process; instructions for setting a first hardware prefetch state on the first processor based on each determined first prefetch status, to correspondingly enable or disable said hardware prefetch; instructions for receiving a second process , comprising successive computational phases, to be executed by a processor in the data processing system; instructions for assigning the second process to run on a second processor; instructions for determining a second prefetch status for the second process at each of successive times when the second process is running, wherein each determined second prefetch status indicates whether hardware prefetch should be enabled or disabled for a next following computational phase of the second process; and instructions for setting a second hardware prefetch state on the second processor based on each determined second prefetch status, to correspondingly enable or disable said hardware prefetch.
22. The computer program product of claim 21 , wherein a hardware prefetch of each processor of said data processing system is individually enabled or disabled, selectively.
23. The computer program product of claim 21 , wherein determining a prefetch status includes examining a prefetch status indicator in a given process.
24. The computer program product of claim 23 , wherein the prefetch status indicator is a bit in a machine status word.
25. The computer program product of claim 21 , wherein setting a hardware prefetch state on a given processor includes writing a machine status word to a machine status register in the given processor.
Unknown
January 8, 2008
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