Multiple Level Cell Memory Device with Single Bit Per Cell, Re-Mappable Memory Block

1. A non-volatile memory device comprising: a memory array having a plurality of memory blocks comprising: a subset of the plurality of memory blocks wherein each memory block of the subset is adapted to operate in either a multiple level cell mode or a single bit per cell mode; and at least one dedicated error free memory block of the plurality of memory blocks that is adapted to operate only in the single bit per cell mode.

2. The device of claim 1 wherein the non-volatile memory device is a NAND flash memory device.

3. The device of claim 1 wherein the dedicated memory block is block 0 of the memory device.

4. The device of claim 1 wherein the dedicated memory block is adapted to store boot code.

5. The device of claim 1 wherein the dedicated memory block is adapted to store defective memory addresses.

6. The device of claim 1 wherein the multiple level cell mode comprises two bits stored on each cell of the block.

7. A flash memory device comprising: a memory array comprising a plurality of memory cells organized into memory blocks including at least one dedicated error free memory block that operates only in a single density mode; and control circuitry for controlling which memory blocks store data in a high density mode and which memory blocks store data in the single density mode.

8. The device of claim 7 and further including: a control bus, coupled to the control circuitry, for accepting configuration commands; and a control register that stores configuration bits in response to the control circuitry and the configuration commands.

9. The device of claim 7 wherein the control circuitry is further adapted to control remapping of a first of the memory blocks to the dedicated memory block such that further accesses to the dedicated memory block are performed by the first memory block.

10. The device of claim 7 and further including: a control bus, coupled to the control circuitry, for accepting single density and high density read and write commands such that the control circuitry writes to and reads from the memory blocks in either the single density mode or the high density mode in response to the commands.

11. A flash memory device having a control bus, an address bus and a data bus, the device comprising: a memory array comprising a plurality of memory cells organized into memory blocks including a first dedicated error free memory block that operates only in a single density configuration, the remaining memory blocks capable of operating in either the single density configuration or a high density configuration; control circuitry, coupled to the control bus, for controlling which memory blocks store data in a high density configuration and which memory blocks store data in the single density configuration; and control registers, coupled to the control circuitry, for storing configuration bits indicating the configuration of each of the memory blocks.

12. The device of claim 11 wherein the flash memory device is a NAND flash memory device.

13. The device of claim 11 wherein the control circuitry remaps access to the first dedicated memory block to a second dedicated memory block that operates only in the single density configuration.

14. A flash memory system comprising: a processor for generating memory control signals; and a flash memory device coupled to the processor and comprising: a memory array having a plurality of memory blocks comprising: a subset of the plurality of memory blocks that are each adapted to operate in either a multiple level cell configuration or a single bit per cell configuration; and at least one dedicated error free memory block of the plurality of memory blocks that is adapted to operate only in the single bit per cell configuration.

15. The system of claim 14 wherein the flash memory device further includes control circuitry, coupled to the processor, for changing the configuration of each memory block in response to the memory control signals.

16. The system of claim 15 wherein the control circuitry further controls access to the dedicated memory block such that accesses to a defective memory block are remapped to the dedicated memory block.

17. A method for accessing a plurality of memory blocks in a flash memory device, the method comprising: performing a single density read operation from a dedicated error free memory block of the plurality of memory blocks, the dedicated error free memory block operating only in a single density configuration; performing a high density write operation to a first memory block of the plurality of memory blocks; and performing a single density write operation to a second memory block of the plurality of memory blocks.

18. The method of claim 17 and further including: performing a single density read operation from the second memory block; and performing a high density read operation from the first memory block.

19. The method of claim 17 wherein performing a single density read operation from the dedicated memory block comprises remapping the read operation to an error free memory block that operates only in the single density configuration.

20. A method for accessing a plurality of memory blocks in a flash memory device that is part of a memory system having a processor, the method comprising: performing a single density read operation from memory block 0 of the plurality of memory blocks, memory block 0 being error free and capable of operating only in a single density configuration; performing a high density write operation to a first memory block of the plurality of memory blocks; and performing a single density write operation to a second memory block of the plurality of memory blocks.

21. The method of claim 20 wherein memory block 0 contains boot code that is executable by the processor.

22. The method of claim 20 wherein memory block 0 contains addresses of bad memory blocks of the plurality of memory blocks.