Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory controller comprising: a. a clock line adapted to convey a clock signal; b. a phase detector having: i. a data strobe node adapted to receive a data strobe signal; ii. a phase lock input node adapted to receive a phase lock signal; and iii. a phase detector output node adapted to provide phase information; iv. wherein the phase detector is adapted to compare the strobe signal with the phase lock signal to produce the phase information; c. a lock circuit having: i. a clock node coupled to the clock line and adapted to receive the clock signal; ii. a lock circuit input node coupled to the phase detector output node and adapted to receive the phase information; iii. a phase lock output node coupled to the phase lock input node and adapted to transmit the phase lock signal; and iv. a sampling signal output node; v. wherein the lock circuit is adapted to provide a data sampling signal on the sampling signal output node; and d. a sampling receiver having: i. a data input terminal adapted to receive a data signal; and ii. a clock input terminal coupled to the sampling signal output node and adapted to receive the data sampling signal; iii. wherein the sampling receiver samples the data signal using the data sampling signal.
2. The memory controller of claim 1 , wherein the data strobe signal and the data signal are edge aligned when transmitted.
3. The memory controller of claim 1 , wherein the lock circuit is a DLL.
4. The memory controller of claim 1 , wherein the lock circuit periodically synchronizes the data strobe and the data sampling signal absent the data signal.
5. The memory controller of claim 1 , wherein the data sampling signal is a continuous periodic signal.
6. The memory controller of claim 5 , wherein the data strobe is an intermittent periodic signal.
7. The memory controller of claim 6 , the lock circuit further comprising a phase control circuit exhibiting a digital state defining a phase relationship between the clock signal and the sampling signal, wherein the phase control circuit holds the state when the strobe signal is absent.
8. The memory controller of claim 1 , further comprising a data timing system storing the digital state and at least one additional digital state, the at least one additional digital state defining a second phase relationship between the clock signal and a second sampling signal.
9. The memory controller of claim 8 , further comprising a multi drop bus interface connectable to a plurality of memory devices, wherein the data timing system stores one of the digital states for each of the plurality of memory devices.
10. An integrated circuit comprising: a. a timing system having: i. a data strobe node adapted to receive a data strobe signal; ii. a clock node adapted to receive a clock signal, wherein the data strobe signal is intermittently active over a period in which the sampling clock signal is active; iii. a sampling signal output node adapted to provide a sampling signal; and iv. phase control circuitry adapted to derive the sampling signal by phase adjusting the clock signal to align the sampling signal with the data strobe signal; and b. a sampling receiver having: i. a data input terminal adapted to intermittently receive a data signal concomitant with the data strobe signal over the period in which the sampling clock signal is active; and ii. a clock input terminal coupled to the sampling signal output node and adapted to receive the sampling clock signal.
11. The integrated circuit of claim 10 , wherein the timing system includes a register adapted to store a digital state representing a phase relationship between the clock signal and the data sampling signal.
12. The integrated circuit of claim 10 , the timing system further comprising: a. a second data strobe node adapted to receive a second data strobe signal; b. a second sampling signal output node adapted to provide a second sampling signal; and c. second phase control circuitry adapted to align the second data strobe signal with the second sampling signal.
13. The integrated circuit of claim 12 , further comprising: a. a first register adapted to store a first digital state representing a first phase relationship between the clock signal and the first mentioned data sampling signal; and b. a second register adapted to store a second digital state representing a second phase relationship between the clock signal and the second data sampling signal.
14. The integrated circuit of claim 13 , further comprising a second sampling receiver having: a. a second data input terminal adapted to receive a second data signal; and b. a second clock input terminal coupled to the second sampling signal output node and adapted to receive the second data sampling signal.
15. The integrated circuit of claim 14 , further comprising: a. a first input/output unit adapted to communicate the first data signal with a first memory device; and b. a second input/output unit adapted to communicate the second data signal with a second memory device.
16. A method comprising: a. generating a periodic data sampling signal; b. receiving a data signal as a serious of data symbols; c. receiving a strobe signal with the data signal, the strobe signal having a signal transition for each of the data symbols, wherein each signal transition has a phase relationship relative to a corresponding one of the symbols; d. aligning the data sampling signal with the received strobe signal; and e. sampling the data symbols with the data sampling signal.
17. The method of claim 16 , wherein aligning the data sampling signal with the received strobe signal includes saving a digital state representative of a second phase relationship between the data sampling signal and a clock signal.
18. The method of claim 16 , further comprising receiving the strobe signal without the data signal and aligning the data sampling signal with the recieved strobe signal.
19. The method of claim 16 , wherein the data signal is received on a data node and the strobe signal is received on a strobe node, the method further comprising transmitting a second data signal as a second series of data symbols on the data node.
20. The method of claim 19 , further comprising transmitting a second strobe signal having a second signal transition for each of the second series of data symbols.
21. The method of claim 20 , wherein the second strobe signal is transmitted on the strobe node.
22. The method of claim 16 , wherein the data strobe signal is intermittently active over a period in which the data sampling signal is active.
23. A method comprising: a. generating a periodic data sampling signal; b. receiving a data signal; c. receiving a timing reference signal with the data signal, the timing reference signal having a phase relationship relative to the data signal; d. aligning the data sampling signal with the received timing reference signal, wherein aligning the data sampling signal with the received timing reference signal includes saving a digital state representative of a second phase relationship between the data sampling signal and a clock signal; e. sampling the data signal with the data sampling signal; f. generating a second periodic data sampling signal; g. receiving a second data signal; h. receiving a second timing reference signal with the second data signal, the second timing reference signal having a second phase relationship relative to the second data signal; i. aligning the second data sampling signal with the received second timing reference signal; and j. sampling the second data signal with the second data sampling signal; k. wherein aligning the second data sampling signal with the received second timing reference signal includes saving a second digital state representative of a third phase relationship between the second data sampling signal and the clock signal.
24. An integrated circuit comprising: a. a clock node receiving a clock signal; b. a timing reference node receiving a strobe signal, wherein the strobe signal is intermittently active over a period in which the clock signal is active; c. a data node receiving a data signal synchronized with the strobe signal, the data signal expressed as a series of symbols each aligned to an edge of the strobe signal; d. means for developing, from the clock signal and the strobe signal, a data sampling signal; and e. means for sampling the data symbols with the data sampling signal.
25. The integrated circuit of claim 24 , wherein the means for developing the data sampling signal aligns the strobe and data sampling signal absent the data signal.
26. The integrated circuit of claim 24 , further comprising a memory circuit issuing the strobe signal and the data signal.
27. The integrated circuit of claim 24 , further comprising means for disabling the data sampling signal when the data signal is absent.
28. The integrated circuit of claim 24 , further comprising means for transmitting a second strobe signal, and means for transmitting a second data signal on the data node and timed to the second strobe signal.
29. The integrated circuit of claim 28 , wherein the means for transmitting the second strobe signal transmits the second strobe signal on the timing reference node.
Unknown
March 25, 2008
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