Configurable Width Buffered Module Having a Bypass Circuit

1. A memory module comprising: a connector interface which includes a first contact, a second contact and a third contact; a first integrated circuit having memory including a first storage cell and a second storage cell; and a buffer device coupled to the first integrated circuit and the connector interface, wherein the buffer device is operable in a first mode and a second mode, wherein: during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact and the second contact, respectively; and during the second mode of operation, at a first time the first storage cell is accessible from the first contact and the second contact is coupled to the third contact.

2. The memory module of claim 1 , wherein: during the second mode of operation, at a second time the second storage cell is accessible from the first contact and the second contact is coupled to the third contact.

3. The memory module of claim 1 , wherein a delay is provided when accessing the first storage cell in the second mode of operation.

4. The memory module of claim 1 , wherein during the first mode of operation, a first coupling circuit couples a first external signal line coupled to the first contact to a first internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a second internal line coupled to the second storage cell.

5. The memory module of claim 1 , wherein during the second mode of operation at the first time, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.

6. The memory module of claim 2 , wherein during the second mode of operation at the second time, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the second storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.

7. The memory module of claim 1 , wherein the buffer device further comprises a multiplexer/demultiplexer circuit coupled to the first and second contacts to access the first and second storage cells.

8. The memory module of claim 1 , wherein the buffer device further comprises a bypass circuit capable to transfer information between the first and third contacts.

9. The memory module of claim 1 , further comprising a fourth contact and wherein the buffer device includes: a first bypass circuit capable to transfer information between the first and fourth contacts: and, a second bypass circuit capable to transfer information between the second and third contacts.

10. The memory module of claim 9 , further comprising a fifth, a sixth, a seventh and a eighth contact and wherein the buffer device includes: a third bypass circuit capable to transfer information between the fifth and seventh contacts: and, a fourth bypass circuit capable to transfer information between the sixth and eighth contacts.

11. The memory module of claim 1 , wherein the first, second and third contacts are pins for mating to a socket.

12. The memory module of claim 1 , wherein in a master device generates a control signal to the memory module to determine the mode of operation.

13. A memory module comprising: a connector interface which includes a first contact, a second contact and a third contact; a first integrated circuit having memory including a first storage cell; a second integrated circuit having memory including a second storage cell; and a buffer device coupled to the first integrated circuit, the second integrated circuit and the connector interface, wherein the buffer device is operable in a first mode and a second mode, wherein: during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact and the second contact, respectively; and during the second mode of operation, at a first time the first storage cell is accessible from the first contact and the second contact is coupled to the third contact.

14. The memory module of claim 13 , wherein: during the second mode of operation, at a second time the second storage cell is accessible from the first contact and the second contact is coupled to the third contact.

15. The memory module of claim 13 , wherein a delay is provided when accessing the first storage cell in the second mode of operation.

16. The memory module of claim 13 , wherein during the first mode of operation, a first coupling circuit couples a first external signal line coupled to the first contact to a first internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a second internal line coupled to the second storage cell.

17. The memory module of claim 13 , wherein during the second mode of operation at the first time, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.

18. The memory module of claim 14 , wherein during the third mode of operation, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the second storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.

19. The memory module of claim 13 , wherein the buffer device further comprises a multiplexer/demultiplexer circuit coupled to the first and second contacts to access the first and second storage cells.

20. The memory module of claim 13 , wherein the buffer device further comprises a bypass circuit capable to transfer information between the first and third contacts.

21. The memory module of claim 13 , further comprising a fourth contact and wherein the buffer device includes: a first bypass circuit capable to transfer information between the first and third contacts: and, a second bypass circuit capable to transfer information between the second and fourth contacts.

22. The memory module of claim 21 , further comprising a fifth, a sixth, a seventh and a eighth contact and wherein the buffer device includes: a third bypass circuit capable to transfer information between the fifth and seventh contacts: and, a fourth bypass circuit capable to transfer information between the sixth and eighth contacts.

23. The memory module of claim 13 , wherein the first, second and third contacts are pins for mating to a socket.

24. The memory module of claim 13 , wherein in a master device generates a control signal to the memory module to determine the mode of operation.

25. A memory module comprising: a first integrated circuit having memory including a first storage cell, a second storage cell and a third storage cell; a plurality of internal signal lines including a first and a second internal signal line coupled to the first integrated circuit; a plurality of external signal lines including a first external signal line, a second external signal line, and a third external signal line; and, a buffer device coupled to the plurality of internal signal lines and the plurality of external signal lines, wherein: at a first time the first storage cell is accessible from the first external signal line coupled to the first internal signal line and the second storage cell is accessible from the second external signal line coupled to the second internal signal line; and at a second time the third storage cell is accessible from the first external signal line coupled to the first internal signal line and the second external signal line is coupled to the third external signal line.

26. The memory module of claim 25 , wherein: at a third time, the third storage cell is accessible from the first external signal line coupled to the second internal signal line and the second external signal line is coupled to the third external signal line.

27. The memory module of claim 25 , wherein a delay is provided when accessing the third storage cell in the second mode of operation.

28. The memory module of claim 25 , wherein the buffer device further comprises a multiplexer/demultiplexer circuit coupled to the first and second external signal lines to access the first, second, and third storage cells.

29. The memory module of claim 25 , wherein the buffer device further comprises a bypass circuit capable to transfer information between the first and third external signal lines.

30. The memory module of claim 25 , wherein the first, second and third external signal lines are coupled to a socket for positioning the memory module.

31. The memory module of claim 25 , wherein in a master device generates a control signal to the memory module to determine the mode of operation.

32. A memory module comprising: a first integrated circuit having memory including a first storage cell and a second storage cell; a second integrated circuit having memory including a third storage cell and a fourth storage cell; a plurality of internal signal lines including a first and a second internal signal line coupled to the first and second integrated circuits; a plurality of external signal lines including a first external signal line, a second external signal line, and a third external signal line; and, a buffer device coupled to the plurality of internal signal lines and the plurality of external signal lines, wherein: at a first time, the first storage cell is accessible from the first external signal line coupled to the first internal signal line and the second storage cell is accessible from the second external signal line coupled to the second internal signal line; and at a second time, the second storage cell is accessible from the first external signal line coupled to the first internal signal line and the second external signal line is coupled to the third external signal line.

33. The memory module of claim 32 , wherein: at a third time, the fourth storage cell is accessible from the first external signal line coupled to the second internal signal line and the second external signal line is coupled to the third external signal line.

34. The memory module of claim 32 , wherein a delay is provided when accessing the second storage cell in the second mode of operation.

35. The memory module of claim 32 , wherein the buffer device further comprises a multiplexer/demultiplexer circuit coupled to the first and second external signal lines to access the first, second, third and fourth storage cells.

36. The memory module of claim 32 , wherein the buffer device further comprises a bypass circuit capable to transfer information between the first and third external signal lines.

37. The memory module of claim 32 , wherein the first, second and third external signal lines are coupled to a socket for positioning the memory module.

38. The memory module of claim 32 , wherein in a master device generates a control signal to the memory module to determine the mode of operation.

39. A buffer device, comprising: a configurable width interface; a multiplexer/demultiplexer circuit capable to access a first storage cell in a plurality of storage cells; and, a first bypass circuit capable to transfer information through the buffer device from a first contact to a second contact.

40. The buffer device of claim 39 , further comprising: second bypass circuit capable to transfer information through the buffer device from a third contact to a fourth contact.

41. The buffer device of claim 40 , further comprising: a third bypass circuit capable to transfer information through the buffer device from a fifth contact to a sixth contact; and, a fourth bypass circuit capable to transfer information through the buffer device from a seventh contact to a eighth contact.

42. A memory module, comprising: a substrate having a first and second surface; a first integrated circuit memory device disposed on the first surface; a buffer device having a configurable width interface; and, a second integrated circuit memory device, wherein the buffer device and second integrated circuit memory device are included in a first package, the first package disposed on the first surface.

43. The memory module of claim 42 , wherein the first package includes a connector coupled to the first surface.

44. The memory module of claim 42 , wherein the buffer device is disposed on a first die and the second integrated circuit memory device is disposed on a second die, wherein the first and second dies are included in the first package.

45. A memory module, comprising: a substrate having a first and second surface; a first integrated circuit memory device disposed on the first surface; a buffer device having a configurable width interface; and, a second integrated circuit memory device, wherein the second integrated circuit memory device is included in a first package and the buffer device is included in a second package, and wherein the second package is disposed on the first surface and the second package is disposed between the first package and the first surface.

46. The memory module of claim 42 , wherein the memory module is a dual inline memory module.

47. The memory module of claim 42 , wherein the first and second integrated circuits are dynamic random access memory (“DRAM”) devices.

48. The memory module of claim 42 , wherein the memory module includes 18 integrated circuit memory devices, wherein 9 integrated circuit memory devices are positioned on the second surface, 6 integrated circuit memory devices are positioned on the first surface, and 3 integrated circuit memory devices are positioned on the buffer device.

49. The memory module of claim 42 , wherein the memory module includes 18 integrated circuit memory devices, wherein 10 integrated circuit memory devices are positioned on the second surface, 6 integrated circuit memory devices are positioned on the first surface, and 2 integrated circuit memory devices positioned with the buffer device, wherein the 2 integrated circuit memory devices and the buffer device are included in a package positioned on the first surface.

50. The memory module of claim 42 , wherein the buffer device includes a bypass circuit.

51. The memory module of claim 42 , wherein the memory module is coupled to a master device.

52. A memory module, comprising: a substrate; a connector interface, coupled to the substrate, which includes a first contact, a second contact and a third contact; a first integrated circuit having memory including a first storage cell and a second storage cell; and a buffer device with the first integrated circuit positioned in a package coupled to the substrate, wherein the buffer device is operable in a first mode and a second mode, wherein: during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact and the second contact, respectively; and during the second mode of operation, at a first time the first storage cell is accessible from the first contact and the second contact is coupled to the third contact.

53. The memory module of claim 52 , wherein: during the second mode of operation, at a second time the second storage cell is accessible from the first contact and the second contact is coupled to the third contact.

54. The memory module of claim 52 , wherein a delay is provided when accessing the first storage cell in the second mode of operation.

55. The memory module of claim 52 , wherein during the first mode of operation, a first coupling circuit couples a first external signal line coupled to the first contact to a first internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a second internal line coupled to the second storage cell.

56. The memory module of claim 52 , wherein during the second mode of operation at the first time, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the first storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.

57. The memory module of claim 52 , wherein during the second mode of operation at the second time, a first coupling circuit couples a first external signal line coupled to the first contact to an internal signal line coupled to the second storage cell; and, a second coupling circuit couples a second external signal line coupled to the second contact to a third external line coupled to the third contact.