Logic Circuit, Timing Generation Circuit, Display Device, and Portable Terminal

1. A logic circuit comprising: a plurality of cascade-connected flip-flops, for generating a plurality of pulse signals whose frequencies are different, in synchronization with a clock signal which is input from external to the logic circuit; and a reset circuit that resets one or more of said flip-flops independently from remaining ones of said flip-flops, wherein said logic circuit is formed on or over an insulating substrate, and wherein a level-shift circuit is formed on said insulating substrate, and level-shifts the clock signal prior to the clock signal being input to the reset circuit.

2. The logic circuit according to claim 1 , wherein said reset circuit takes the clock signal as an input, and generates separate reset signals at least partially based on the timing of the clock signal.

3. The logic circuit according to claim 1 , wherein there are at least three flip-flops cascade-connected.

4. A timing generation circuit comprising: a plurality of cascade-connected flip-flops, for generating a plurality of pulse signals whose frequencies are different, in synchronization with a clock signal; and a reset circuit that resets one or more of said flip-flops independently from remaining ones of said flip-flops, wherein said timing generation circuit is formed on or over an insulating substrate, and wherein a level-shift circuit is formed on said insulating substrate, and level-shifts the clock signal prior to the clock signal being input to the reset circuit.

5. The timing generation circuit according to claim 2 , wherein said reset circuit takes the clock signal as an input, and generates separate reset signals at least partially based on the timing of the clock signal.

6. The timing generation circuit according to claim 2 , wherein there are at least three flip-flops cascade-connected.

7. A timing circuit comprising: a plurality of flip-flops, for generating a plurality of pulse signals whose frequencies are different, in synchronization with a clock signal; and a reset circuit that takes said clock signal as an input, and which independently resets each of said flip-flops, at different timings, at least partially based upon the timing of said clock signal, wherein said timing circuit is formed on or over an insulating substrate, and wherein a level-shift circuit is formed on said insulating substrate, and level-shifts the clock signal prior to the clock signal being input to the reset circuit.

8. The timing generation circuit according to claim 7 , wherein there are at least three flip-flops cascade-connected.