Methods and Systems for Locally Generating Non-Integral Divided Clocks with Centralized State Machines

1. A method for locally generating a ratio clock on a chip, comprising: generating a global clock signal having a global clock cycle; providing a centralized state machine, the state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter, the control signal being provided to multiple local clock generation circuits; providing the control signal to staging latches, the staging latches generating a clock high signal and a clock low signal, providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

2. The method of claim 1 wherein the state machine is partially centralized.

3. The method of claim 1 wherein the clock high and clock low signal have patterns derived from a waveform of a target divided ratio clock, the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle.

4. The method of claim 1 wherein the clock low signal and clock high signal are determined from a target ratio clock.

5. The method of claim 1 wherein the staging latches are localized staging latches being part of local clock generation circuits.

6. The method of claim 1 wherein the staging latches are partially centralized staging latches providing the clock high signal and the clock low signal to a plurality of local clock generation circuits.

7. The method of claim 1 wherein the state machine and the staging latches are partially centralize such that each state machine and staging latches providing the clock high signal and the clock low signal to a portion of local clock generation circuits on the chip.

8. The method of claim 1 wherein the state machine and the staging latches are arranged in a hierarchy, the state machine providing control signals to a plurality of partially centralized staging latches, each staging latch providing the clock high signal and the clock low signal to a portion of local clock generation circuits on the chip.

9. The method of claim 1 wherein the staging latches are localized staging latches being part of local clock generation circuits and the state machine is partially centralized such that multiple state machines provide control signals to groups of local clock generation circuits.

10. The method of claim 1 wherein the frequency and duty cycle of the ratio clock may be dynamically changed without changing the designs of local circuiting by selecting patterns for the clock low signal and the clock high signal.

11. A method for locally generating a ratio clock, comprising: generating a global clock signal having a global clock cycle; providing a centralized clock control unit including a first state machine and a second state machine, the first state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the first state machine generating a clock high signal having a pattern corresponding to a target divided ratio clock when the global clock is high; providing the second state machine with a counter going through a complete cycle in response to a non-integer number of global clock cycles, the second state machine generating a clock low signal having a pattern corresponding to the target divided ratio clock when the global clock is low; providing local pass gate for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

12. The method of claim 11 wherein the state machine is partially centralized.