RF Backscatter Transmission with Zero DC Power Consumption

1. In a transmitter-receiver circuit, for transmitting and receiving through an antenna, a method of minimizing power consumption comprising: setting an antenna load impedance to match the impedance of the antenna; and varying the antenna load impedance between a short impedance and a matching impedance, wherein the circuit is capable of operating in backscatter mode; wherein the varying step includes varying the antenna load impedance in the range between short impedance, matching, and open impedance.

2. The method of claim 1 wherein the varying step comprises switching the short and the matching impedances into and out of the circuit.

3. The method of claim 2 wherein the switching step includes applying a voltage to the gate of a FET.

4. The transmitter-receiver circuit of claim 1 wherein the circuit is capable of half-duplex communication.

5. A transmitter-receiver circuit comprising: a transmitter-receiver for transmitting and receiving through an antenna having an impedance; switching logic coupled between the antenna and the transmitter-receiver, the switching logic adapted to establish an antenna load impedance which matches the antenna impedance during a listening portion of a half-duplex cycle, and, during the transmit portion of the half-duplex cycle, and, to vary the antenna load impedance between a short and a match to the antenna impedance, wherein the transmitter-receiver is capable of operating in backscatter mode; and generating a baseband having a phase and magnitude and varying the phase and magnitude thereof.

6. The transmitter-receiver circuit of claim 5 wherein the transmitter-receiver is a half-duplex transmitter-receiver.

7. A transmitter-receiver circuit, as recited in claim 5 , wherein the switching logic includes a Field Effect Transistor (FET) having a gate to which voltage is applied for causing the establishing of the load impedance.

8. A transmitter-receiver circuit, as recited in claim 5 , wherein the FET is N-channel, P-channel, enhancement or depletion mode transistor.

9. A transmitter-receiver circuit, as recited in claim 5 , wherein the FET is a MOSFET, IgFET or JFET transistor.

10. A transmitter-receiver circuit, as recited in claim 5 , wherein the FET is made of silicon, GaAs, InFaAs, SOI, or plastic transistors.

11. A transmitter-receiver circuit comprising: a transmitter-receiver for transmitting and receiving through an antenna capable of operating in half-duplex mode at a baseband having a phase and a magnitude; and logic for varying the magnitude and the phase of the baseband as applied to the antenna, wherein the transmitter-receiver is capable of operating in backscatter mode; wherein the logic can vary the antenna load impedance in the range between short impedance, matching, and open impedance.

12. The transmitter-receiver circuit of claim 11 further including switching logic coupled between the antenna and the transmitter-receiver for varying an antenna load impedance in accordance with portions of the half-duplex cycle.

13. A transmitter-receiver circuit, as recited in claim 11 , further including an antenna.

14. A transmitter-receiver circuit, as recited in claim 11 , wherein the transmitter-receiver is a half-duplex transmitter-receiver.

15. A transmitter-receiver circuit, as recited in claim 11 , wherein the logic includes a Field Effect Transistor (FET) having a gate to which voltage is applied.

16. A transmitter-receiver circuit, as recited in claim 15 , wherein the FET is N-channel, P-channel, enhancement or depletion mode transistor.

17. In a transmitter-receiver circuit, for transmitting and receiving through an antenna, a method of minimizing power consumption comprising: setting an antenna load impedance to match the impedance of the antenna; varying the antenna load impedance between a short impedance and a matching impedance, wherein the circuit is capable of operating in backscatter mode; and generating a baseband having a phase and magnitude and varying the phase and magnitude thereof.