Performing an N-Bit Write Access to an Mxn-Bit-Only Peripheral

1. A computer system, comprising: an N-bit Digital Signal Processor (DSP) that generates an N-bit write transaction for modifying an N-bit word at an 2×N-bit data location of an N-bit peripheral; a first bus including an N-bit wide data bus, coupled to the N-bit DSP; at least one peripheral including a 2×N-bit-only peripheral, the 2×N-bit-only peripheral having data locations, each data location having a width of 2×N bits, the 2×N-bit-only peripheral being incapable of accepting any N-bit write transactions; a second bus including a 2×N bit wide data bus, coupled to the 2×N-bit-only peripheral; and a bridge coupled between the first bus and the second bus, the bridge including a write merge system, the write merge system including: first logic circuits for receiving new N-bit wide data and for receiving an N-bit write transaction from the N-bit DSP, the N-bit write transaction being for modifying an N-bit word of a 2×N-bit word at a 2×N-bit data location of the 2×N-bit-only peripheral, and second logic circuits for writing a 2×N-bit word to said 2×N-bit data location of the 2×N-bit-only peripheral, the 2×N-bit word including said N-bit word modified by the new N-bit wide data, in which the second logic circuits perform a single write of 2×N bits that changes only said N-bit word that was being modified by the N-bit write transaction.

2. The computer system of claim 1 , in which the write merge system writes the 2×N-bit word to said 2×N-bit data location of the 2×N-bit-only peripheral without any software intervention by the N-bit DSP subsequent to receiving said write transaction.

3. The computer system of claim 1 , in which the write merge system includes a memory map in which is pre-stored address ranges of peripherals, and window select registers in which are pre-stored most significant bits associated with each address range.

4. The computer system of claim 3 , in which the write transaction includes a P-bit wide address, and in which said data location of the 2×N-bit-only peripheral has a Q-bit wide address, and in which the first logic circuits produce a Q-bit wide address from the P-bit wide address, from the memory map, and from the window select registers.

5. The computer system of claim 1 , including a circuit-supporting substrate and in which the computer system is a System-on-Chip, and in which the DSP, at least a portion of the first bus, at least a portion of the second bus, the bridge, and the at least one peripheral are disposed on the circuit-supporting substrate.

6. The computer system of claim 1 , in which the first logic circuits read the 2×N-bit word from the 2×N-bit-only peripheral, and in which the 2×N-bit word that was read includes the N-bit word being modified as a result of the N-bit write transaction from the N-bit DSP.

7. The computer system of claim 6 , in which the second logic circuits include a read state machine, a high read data queue coupled to the read state machine, a low read data queue coupled to the read state machine, at least one multiplexer coupled to the read state machine, and a write state machine coupled to the at least one multiplexer.

8. The computer system of claim 7 , in which the 2×N-bit word that was read includes a high N-bit word and a low N-bit word, and in which the high N-bit word is stored in the high read data queue and the low N-bit word is stored in the low read data queue.

9. The computer system of claim 8 , in which the 2×N-bit word that was read is a 32-bit word and includes a high 16-bit word and a low 16-bit word, and in which the high 16-bit word is stored in the high read data queue and the low 16-bit word is stored in the low read data queue.

10. The computer system of claim 7 , in which the at least one multiplexer merges the new N-bit wide data with the 2×N-bit word that was read, to form a modified 2×N-bit word at an output of the at least one multiplexer.

11. The computer system of claim 10 , in which the second logic circuits write the modified 2×N-bit word to said data location of the 2×N-bit-only peripheral from a single N-bit DSP write transaction.

12. The computer system of claim 1 , in which the single write of 2×N bits performed by the second logic circuits does not change the other N-bit word of the 2×N-bit word at said 2×N-bit data location of the 2×N-bit peripheral.

13. A write merge system for bridging a first bus including a first data bus of N-bit width and a first address bus of P-bit width with a second bus including a second data bus of M×N-bit width, where M is greater than or equal to 2, and a second address bus of Q-bit width, comprising: means for receiving an address of P-bit width from the first bus; means for receiving new data of N-bit width from the first bus; means for convening the address of P-width to a modified address of Q-bit width; means for reading old data of M×N bit width from the second bus; means for merging the received new data of N-bit width with the read old data of M×N-bit width to create a modified data of M×N-bit width; and means for writing to the second bus the modified address of Q-bit width and the modified data of M×N-bit width.

14. The write merge system of claim 13 , including an N-bit processor coupled to the first data bus and at least one M×N-bit-only peripheral coupled to the second data bus.

15. The write merge system of claim 14 , in which the M×N-bit-only peripheral has an address of Q-bit width, where Q>P.

16. In a computer system, including a two-cycle access N-bit processor, at least one M×N-bit-only peripheral and a write merge system coupled to the two-cycle access N-bit processor and to the at least one M×N-bit-only peripheral, a method of modifying a N-bit word of a M×N-bit data location of the M×N-bit-only peripheral using only two clock cycles of the two-cycle access N-bit processor, comprising the following steps performed at the merge write system: a) pre-storing a memory map of addresses of peripherals; b) receiving during a first clock cycle of a two-cycle access N-bit processor, a write transaction, including a P-bit address, to modify a N-bit word of a M×N-bit data location of a M×N-bit-only peripheral with a new N-bit word; c) receiving during a second clock cycle of the two-cycle access N-bit processor, data for the new N-bit word; d) forming a Q-bit address from the P-bit address and from the memory map; e) reading a M×N-bit word from the M×N-bit data location of the M×N-bit-only peripheral; f) merging the new N-bit word with the M×N-bit word read in step e, to create a modified M×N-bit word; and g) writing the modified M×N-bit word to the M×N-bit data location of the M×N-bit-only peripheral.

17. The method of claim 16 , in which N=16.

18. The method of claim 16 , in which M=2.

19. The method of claim 16 , in which P<Q.

20. The method of claim 19 , in which P=7 and Q=12.