Vector Co-Processor for Configurable and Extensible Processor Architecture

1. A microprocessor, comprising: an instruction fetch unit that is adapted to successively fetch first and second instructions from adjacent locations in a common program memory, wherein the first instruction is one of a non-VLIW instruction with an instruction length corresponding to a first number of bits and a VLIW instruction with an instruction length corresponding to a second number of bits, the VLIW instruction comprising a plurality of instruction slots, each slot specifying an independent operation, and wherein the second instruction is the other of the non-VLIW instruction and the VLIW instruction, and wherein the first number of bits and second number of bits are different, and wherein a total number of bits contained in the adjacent memory locations in the common program memory is substantially equal to the sum of the first and second number of bits; an instruction decode unit that is adapted to decode both the fetched non-VLIW instruction and the fetched VLIW instruction, wherein the instruction decode unit examines the first number of bits to decode the fetched non-VLIW instruction, and wherein the instruction decode unit examines the second different number of bits to decode the fetched VLIW instruction; a core processor that executes the fetched non-VLIW instruction; and a co-processor that executes the fetched VLIW instruction, wherein a determination of whether to decode and execute the fetched first and second instructions as non-VLIW and VLIW instructions is based on contents of the fetched first and second instructions.

2. The microprocessor according to claim 1 , wherein the co-processor includes a plurality of multipliers, and wherein the plurality is a configurable number such that a first configured one of the microprocessor includes a first plurality of co-processor multipliers and a second configured one of the microprocessor includes a second different plurality of multipliers.

3. The microprocessor according to claim 1 , wherein the co-processor includes at least one MAC unit that performs a multiply/accumulate operation specified by one of the slots in substantially one cycle of the co-processor.

4. The microprocessor according to claim 1 , further comprising an alignment register file for supporting the execution of unaligned loads from, and stores to, a local memory in substantially one cycle of the co-processor.

5. The microprocessor according to claim 1 , further comprising a select register file for supporting the arbitrary re-arrangement of data from a source vector register into a destination vector register.

6. The microprocessor according to claim 1 , further comprising a vector register having a third number of bits, wherein the VLIW instructions include a load instruction that, during its execution by the co-processor, loads data comprising a fourth number of bits from a local memory, the fourth number of bits being less than the third number of bits, wherein the execution of the load instruction further performs an automatic one of a sign extend and a zero extend of data that is stored in and loaded from the local memory so as to fill the vector register with sign extended or zero extended data comprising the third number of bits.

7. The microprocessor according to claim 1 , further comprising a vector register adapted to store a plurality of complex numbers in an interleaved format such that each of the real components of the complex numbers is stored adjacent to imaginary components of the complex numbers and vice-versa, wherein the VLIW instructions include a complex multiply instruction that, during its execution by the co-processor, performs a multiplication using the complex numbers stored in the vector register.

8. The microprocessor according to claim 1 , wherein each of the VLIW instructions is capable of operating upon a vector operand in SIMD fashion.

9. The microprocessor according to claim 1 , wherein the co-processor is capable of performing multiplication of real numbers, the computation of a real component of a multiplication of complex numbers and the computation of an imaginary component of a multiplication of complex numbers using the same multiplier hardware over a plurality of cycles in an iterative fashion with a single execution of one and only one fetched VLIW instruction.

10. The microprocessor according to claim 1 , wherein the co-processor is capable of performing a multiply operation of a plurality of different multiplicand pairs in one processor cycle.

11. The microprocessor according to claim 1 , wherein the microprocessor is capable of executing the fetched non-VLIW instruction and the fetched VLIW instruction in sequence without requiring a change of processor state.

12. The microprocessor according to claim 11 , wherein instruction words comprising the non-VLIW instructions and the VLIW instructions include a common portion that encodes information indicating whether the instruction words contain either non-VLIW or VLIW instructions.

13. The microprocessor according to claim 1 , wherein one of the non-VLIW instructions can be included in one of the slots of the VLIW instructions.

14. The microprocessor according to claim 1 , wherein the core processor also executes third instructions each having a third number of bits less than the first number of bits and capable of specifying the performance of only a single operation.

15. The microprocessor according to claim 1 , further comprising a vector register that stores a configurable number of scalar operands.

16. The microprocessor according to claim 15 , wherein the co-processor includes a MAC unit that contains half the configurable number of multipliers as the configurable number of scalar operands in the vector register.

17. The microprocessor according to claim 1 , further comprising a plurality of vector registers, and wherein the co-processor includes a select unit that rearranges data from first ones of the vector registers into second ones of the vector registers in accordance with selection control information.

18. The microprocessor according to claim 17 , wherein the selection control information is obtained from an immediate instruction operand.

19. The microprocessor according to claim 17 , wherein the immediate operand is one of a plurality of commonly used selection control values.

20. The microprocessor according to claim 17 , further comprising a select register, and wherein the selection control information is obtained from the select register.

21. The microprocessor according to claim 1 , wherein the independent operation includes one of a MAC operation, an ALU/shift operation and a load/store operation.

22. The microprocessor according to claim 21 , wherein the MAC operation includes a simultaneous multiplication of a plurality of scalar operands in SIMD