Error Detection and Correction Scheme for a Memory Device

1. A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising: reading data from the memory array; performing first and second error detection operations, each performed substantially in parallel with the other on the read data; reporting results of the first and the second error detection operations to the controller; if the first error detection operation detects an error correctable by a first error correction operation and the second error detection operation detects an error, correcting the error with the first error correction operation; and performing the second error detection operation again on the data corrected by the first error correction operation.

2. The method of claim 1 wherein the first error detection operation is a Hamming code error detection and the second error detection operation is a Reed-Solomon code error detection.

3. The method of claim 1 wherein the first and second error detection operations are performed while reading the data from the memory array.

4. The method of claim 1 and further including storing the data in the data buffer.

5. The method of claim 1 and further including: if the data still has the error after the second error detection operation, correcting the error with a second error correction operation.

6. The method of claim 1 and further including: if the first error detection operation detects an error that is uncorrectable by a first error correction operation and the second error detection operation detects an error, correcting the error with a second error correction operation.

7. The method of claim 1 and further including: if the first error detection operation does not detect an error and the second error detection operation detects an error, correcting the error with a second error correction operation.

8. A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising: reading data from the memory array; performing a Hamming code and a Reed-Solomon code error detection operation substantially in parallel; reporting results of the Hamming code and the Reed-Solomon code error detection operations to the controller; and storing the data in the data buffer.

9. The method of claim 8 and further including: if the Hamming code error detection operation detects an error that is uncorrectable by a Hamming code error correction operation and the Reed-Solomon code error detection operation detects an error, correcting the error with a Reed-Solomon code error correction operation.

10. The method of claim 8 and further including: if the Hamming code error detection operation does not detect an error and the Reed-Solomon code error detection operation detects an error, correcting the error with a Reed-Solomon code error correction operation.

11. The method of claim 8 and further including: if the Hamming code error detection operation detects an error correctable by a Hamming code error correction operation and the Reed-Solomon code error detection operation detects an error, correcting the error with the Hamming code error correction operation; and performing the Reed-Solomon code error detection operation again on the data corrected by the Hamming code error correction operation.

12. The method of claim 11 and further including: if the data still has the error after the Reed-Solomon code error detection operation, correcting the error with a Reed-Solomon code error correction operation.

13. A memory device comprising: a NAND-type flash memory array; a data buffer; a controller circuit that is capable of reading data from the memory array and storing the read data in the data buffer; a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit; and a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.

14. The memory device of claim 13 wherein the memory array is a NOR-type flash memory array.

15. The memory device of claim 13 wherein the first error detection and correction routine is a Hamming code error detection and correction routine.

16. The memory device of claim 13 wherein the second error detection and correction routine is a Reed-Solomon code error detection and correction routine.

17. A memory device comprising: a memory array; a data buffer; and a controller circuit that is capable of reading data from the memory array and storing the data in the data buffer; the controller executing a Hamming code error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit, the controller further executing, in parallel with the Hamming code error detection and correction routine, a Reed-Solomon code error detection and correction routine that detects errors in the read data and communicates a second error detection result to the controller circuit.

18. An electronic system comprising: a processor that generates control signals for the electronic system; and a memory device comprising: a NAND-type flash memory array; a data buffer; a controller circuit that is capable of reading data from the memory array and storing the read data in the data buffer; a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit; and a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.