Sense Mechanism for Microprocessor Bus Inversion

1. A sense mechanism for data bus inversion, comprising: a first memory device that stores bits of N-bit bus in a previous bus cycle; and an analog adder that compares said bits of said N-bit bus in said previous bus cycle with bits of said N-bit bus in a current bus cycle and that provides a data inversion signal indicative of whether more than half of said bits of said N-bit bus have changed state, wherein said analog adder comprises: a logic comparison circuit that compares said bits of said N-bit bus in said previous bus cycle with said bits of said N-bit bus in said current bus cycle and that provides a plurality of changed state bits; and an analog sense amplifier that provides said data inversion signal based on said plurality of changed state bits, wherein said analog sense amplifier comprises: a first voltage divider network that divides a first voltage referenced to a common voltage into a weight voltage at a weight node, said weight voltage being one of a plurality of discrete voltage levels indicative of a number of said plurality of changed state bits being asserted, said first voltage divider network comprising: at least one activated first P-channel device coupled between said weight node and said first voltage; and N equivalent-sized first N-channel devices coupled between said weight node and said common voltage, each having a gate receiving a corresponding one of said plurality of changed state bits; a reference circuit that provides a reference voltage relative to said first voltage and indicative of more than half of said plurality of changed state bits being asserted; and a comparator that compares said reference voltage with said weight voltage and that provides said data inversion signal.

2. The sense mechanism of claim 1 , further comprising: said first memory device comprising a first register having an output providing said bits of said N-bit bus in said previous bus cycle; and a second register having an input coupled to said output of said first register and an output that provides said bits of said N-bit bus in said current bus cycle.

3. The sense mechanism of claim 1 , further comprising a plurality of exclusive-OR gates that combine said data inversion signal with each said bit of said N-bit bus in said current bus cycle to perform bus inversion.

4. The sense mechanism of claim 1 , wherein said logic comparison circuit comprises a plurality of exclusive-OR gates which compare said bits of said N-bit bus in said previous bus cycle with said bits of said N-bit bus in said current bus cycle on a bit-by-bit basis for providing said plurality of changed state bits.

5. The sense mechanism of claim 1 , wherein said reference circuit comprises a second voltage divider network which further comprises: a number of activated second P-channel devices coupled between said reference node and said first voltage, wherein said number is equal to the number of said at least one activated first P-channel device; N equivalent-sized second N-channel devices coupled between said reference node and said common voltage level, wherein half of said second N-channel devices are turned on and the other half are turned off; and a half-sized activated N-channel device coupled between said reference node and said common voltage.

6. The sense mechanism of claim 1 , said N-bit bus having N data bits, wherein said reference circuit provides said reference voltage at a voltage level in between a first discrete voltage level representing N/2 changed state bits and a second discrete voltage level representing N/2+1 changed state bits.

7. A microprocessor, comprising: a chip including an external data bus and data logic providing a plurality of internal data bits for each bus cycle; at least one bus state sense mechanism and inverter provided on said chip, each having an input coupled to said data logic and an output coupled to said external data bus, and each said bus state sense mechanism and inverter comprising: a first memory device that stores said plurality of internal data bits from a prior bus cycle; an analog adder that compares said plurality of stored internal data bits from said prior bus cycle with said plurality of internal data bits in a current bus cycle and that provides a data inversion signal to said external data bus indicative of whether more than half of said internal data bits have changed state,said analog adder comprising: a data change sensor having a first input coupled to said logic for receiving said plurality of internal data bits in said current bus cycle, a second input coupled to said first memory device for receiving said plurality of internal data bits from said prior bus cycle, and an output providing a plurality of data change bits; a reference circuit having a reference node that develops a reference voltage relative to a source voltage, said reference voltage indicative of more than half of said plurality of internal data bits changing state from said prior bus cycle to said current bus cycle; a voltage divider network, coupled to said source voltage, having an input receiving said plurality of data change bits and an intermediate weight node that develops a weight voltage relative to said source voltage and indicative of the number of said plurality of data change bits that are asserted; and a comparator that compares said reference voltage with said weight voltage and that provides said data inversion signal; and a bus inverter having an input receiving said plurality of internal data bits in said current bus cycle and an output coupled to said external data bus, wherein said bus inverter selectively inverts said plurality of internal data bits in said current bus cycle based on said data inversion signal.

8. The microprocessor of claim 7 , wherein said bus inverter comprises a plurality of exclusive-OR gates, each having a first input receiving said data inversion signal, a second input receiving a corresponding one of said internal data bits in said current bus cycle and an output providing an output data bit for said external data bus.

9. The microprocessor of claim 7 , wherein said first memory device comprises a register.

10. The microprocessor of claim 7 , said external data bus comprising N bits, wherein said voltage divider network comprises: at least one first P-channel device coupled between said source voltage and said weight node, each being turned on; and N equivalent-sized first N-channel devices coupled between said weight node and ground and each being turned on or off based on a corresponding one of said plurality of data change bits.

11. The microprocessor of claim 10 , wherein said reference circuit comprises: at least one first P-channel device coupled between said source voltage and said reference node, each being turned on; N equivalent-sized second N-channel devices coupled between said reference node and ground including N/2 second N-channel devices that are turned on and N/2 second N-channel devices that are turned off; and a half-bit N-channel device with a width that is half that of said N equivalent-sized N-channel devices, said half-bit N-channel device being coupled between said reference node and ground and being turned on.

12. The microprocessor of claim 7 , wherein said external data bus is divided into a plurality of groups and wherein said at least one bus state sense mechanism and inverter includes one for each of said plurality of groups of said external data bus.

13. A method of data bus inversion, comprising: determining a number of bits of a data bus that change state between bus cycles; converting the number of bits that change state to a corresponding weight voltage, wherein said converting the number of bits that change state to a corresponding weight voltage comprises activating a voltage divider device of a first voltage divider network for each of the number of bits that change state to select a corresponding one of a plurality of discrete voltage levels as the weight voltage; providing a reference voltage indicative of more than half of the bits of the data bus changing state, wherein said providing a reference voltage comprises pre-programming voltage divider devices of a second voltage divider network with substantially similar voltage divider devices as the first voltage divider network to generate the reference voltage at a voltage level between a first of the plurality of discrete voltage levels corresponding to one-half of the data bits changing state and a second of the plurality of discrete voltage levels corresponding to one-half of the data bits changing state plus one; comparing the weight voltage with the reference voltage; and inverting the data bus if more than half of the bits of the data bus change state.

14. The method of claim 13 , wherein said determining a number of bits of a data bus that change state between bus cycles comprises: storing the bits of the data bus for each bus cycle; and comparing the stored bits of the data bus from a prior cycle with corresponding bits of the data bus from a subsequent bus cycle.

15. The method of claim 14 , wherein said comparing the stored bits of the data bus from a prior cycle with corresponding bits of the data bus from a subsequent bus cycle comprises exclusive-ORing each bit from the prior bus cycle with a corresponding bit from the subsequent bus cycle.