Apparatus and Method for Processing a Sequence of Jump Instructions

1. Apparatus for processing a sequence of instructions, which are stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined, by the logical address space, and wherein a return jump instruction is provided to terminate a sub-sequence of instructions started by the jump instruction, comprising: a reader for reading in an instruction of the sequence of instructions; an examiner for examining the read instruction, wherein the examiner is formed to determine and store return jump information on a stack, when the examined instruction is a jump instruction, the return jump information referring to the presently current physical memory window, and to retrieve a predetermined amount of stored return jump information from a stack, when the examined instruction is a return jump instruction; and a decoder for decoding the predetermined amount of stored return jump information retrieved from the stack to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window, wherein the decoder is formed to activate the examiner, when the predetermined amount comprises a reference to a physical address outside of a current physical memory window, and wherein the examiner is formed to retrieve another amount of stored return jump information from the stack to identify the physical address outside of a current physical memory window for a return jump, when the examiner is activated by the decoder.

2. The apparatus according to claim 1 : wherein further another jump instruction is provided, which comprises information for a logical address, to address an instruction, which is positioned in the physical memory window defined by the logical address space; wherein the examiner is formed to determine and store further return jump information in the case of the presence of another jump instruction, which refer to a presently current logical address space; and wherein the decoder the predetermined amount of the stored return jump information is further formed to determine whether the predetermined amount refers to a logical address in the current physical memory window which is suitable for a return jump.

3. The apparatus according to claim 2 , further comprising: a memory management unit for converting the information of the jump instruction or the further jump instruction into a physical address.

4. The apparatus according to claim 2 , wherein the examiner is formed to determine a logical address as re-jump information for the further jump instruction, by using which the sequence of instructions can be continued after a return jump instruction.

5. The apparatus according to claim 3 , wherein the memory management unit is formed to use a descriptor, which identifies a physical address in the physical memory window, so that a physical address can be determined by using the descriptor and a logical address in the logical address space.

6. The apparatus according to claim 5 , wherein the memory management unit is formed to use at least two different descriptors for a logical address space, so that the physical memory window defined by the logical address space comprises uncontiguous physical memory areas, wherein every physical memory area is associated to a segment of the logical address space.

7. The apparatus according to claim 6 , wherein one segment of the logical address space is defined as a Far segment, such that only a jump to a logical address in this segment leads to a change of the memory area by using the jump instruction.

8. The apparatus according to claim 7 , wherein the decoder is formed to activate the examiner to retrieve further region information, in the case where the predetermined amount of return jump information is a logical address in the Far segment.

9. The apparatus according to claim 8 , wherein the decoder is formed to further activate the examiner, when the predetermined amount comprises a window change indicator.

10. The apparatus according to claim 1 : wherein the sequence of instructions comprises a main program, wherein the main program comprises a call for calling a sub-program, and wherein a return instruction is disposed at the end of the sub-program; and wherein the call instruction can be realized by the jump instruction or the further instruction and the return instruction by the return jump instruction.

11. The apparatus according to claim 1 , wherein the information about a physical address of the jump instruction comprises a logical address and a descriptor for identifying a physical memory area.

12. The apparatus according to claim 1 , wherein the examiner is formed to generate a window change indicator and to add it to the return jump information for the jump instruction.

13. The apparatus according to claim 12 , wherein the examiner is formed to determine a descriptor for identifying a physical memory area as well as a logical address, in addition to the window change indicator, to continue the sequence of instructions after a return jump instruction by using the logical address and the descriptor.

14. The apparatus according to claim 12 , wherein the window change indicator refers to one or several predetermined addresses of the logical address space, to which no jump takes place by definition.

15. The apparatus according to claim 1 , which further comprises a stack memory for storing the return jump information, wherein the stack memory is organized as last-in-first-out memory.

16. The apparatus according to claim 1 , wherein the predetermined amount of the stored return jump information is equal to an amount of information, which represent a logical address in the logical address space.

17. The apparatus according to claim 1 , wherein the logical address space comprises 64 kByte, wherein a logical address comprises 2 bytes, wherein the predetermined amount comprises 2 bytes, and wherein the further amount comprises 1 byte or several bytes.

18. Method for processing a sequence of instructions, which are stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined by the logical address space, and wherein a return jump instruction is provided, to terminate a sub-sequence of instructions started by the jump instruction, comprising: reading-in an instruction of the sequence of instructions; examining the read instruction to determine and store return jump information on a stack, when the examined instruction is a jump instruction, the return jump information referring to a presently current physical memory window, retrieving a predetermined amount of stored return jump information from the stack, when the examined instruction is a return jump instruction; decoding the predetermined amount of the stored return jump information retrieved from the stack, to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window; and when the predetermined amount comprises a reference to a physical address outside of a current physical memory window, retrieving a further amount of the stored return jump information from the stack to identify the physical address outside of a current physical memory window for a return jump.

19. An apparatus for processing a sequence of instructions comprising a main program, wherein the main program comprises a call for calling a sub-program, the instructions being stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined by the logical address space, and wherein a return instruction is provided to terminate the sub-program, wherein a further jump instruction is provided, which comprises information for a logical address to address an instruction, which is positioned in the physical memory window defined by the logical address space, comprising: a reader for reading in an instruction of the sequence of instructions; an examiner for examining the instruction, wherein the examiner is formed to determine and store return information in the case of the presence of the jump instruction, the return information referring to the presently current physical memory window, wherein the examiner is formed to determine and store further return information in the case of the further jump instruction, the further return information referring to a presently current logical address space, and to retrieve a predetermined amount of the stored return information in the case of a return instruction; a decoder for decoding the predetermined amount of stored return information to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window, or whether the predetermined amount refers to a logical address in the current physical memory window being suitable for a return, and to activate the examiner in such a case, to retrieve another amount of the stored return information to identify the physical address outside of a current physical memory window for return; and a memory management unit for converting the information of the jump instruction or the further jump instruction into a physical address, wherein the memory management unit is formed to use a descriptor, which identifies a physical address in the physical memory window, so that a physical address is determined by using the descriptor and a logical address in the logical address space, wherein the memory management unit is formed to use at least two different descriptors for a logical address space, so that the physical memory window defined by the logical address space comprises non-contiguous physical memory areas, wherein every physical memory area is associated to a segment of the logical address space, and wherein one segment of the logical address space is defined as a Far segment, such that only a jump to a logical address in the Far segment leads to a change of the memory area by using the jump instruction.

20. An apparatus for processing a sequence of instructions, which are stored at different memory addresses in a physical address space, wherein the apparatus is formed to address a logical address space by a predetermined number of logical addresses, and wherein the physical address space is larger than the logical address space, wherein a first jump instruction comprises a physical address to address an instruction, which is positioned outside of a physical memory window defined by the logical address space, and wherein a return jump instruction is provided to terminate a sub-sequence of instructions started by the first jump instruction, comprising: a reader for reading in an instruction of the sequence of instructions; an examiner for examining the read instruction, wherein the examiner is formed to determine and store return jump information on a stack, when the examined instruction is the first jump instruction, the return jump information referring to the presently current physical memory window, and to retrieve a predetermined amount of stored return jump information from a stack, when the examined instruction is a return jump instruction; and a decoder for decoding the predetermined amount of stored return jump information retrieved from the stack to determine whether the predetermined amount comprises a reference to a physical address outside of a current physical memory window, wherein the decoder is formed to activate the examiner when the predetermined amount comprises a reference to a physical address outside of a current physical memory window, and wherein the examiner is formed to retrieve another amount of stored return jump information from the stack to identify the physical address outside of a current physical memory window for a return jump, when the examiner is activated by the decoder, wherein a second jump instruction is provided, which comprises information for a logical address, which is positioned in the physical memory window defined by the logical address space, wherein the examiner is formed to determine and store second return jump information in the presence of the second jump instruction, the second return jump information referring to a current logical address space, and wherein the decoder is formed to determine, whether the predetermined amount refers to a logical address in the current physical memory window which is suitable for a return jump; a memory management unit for converting the information of the jump instruction or the second jump instruction into a physical address, wherein the memory management unit is formed to use at least two different descriptors, identifying physical addresses in the physical memory window, a physical address being determined by using a descriptor and a logical address in the logical address space, wherein the physical memory window defined by the logical address space comprises non-contiguous physical memory areas, and wherein every physical memory area is associated to a segment of the logical address space, and wherein one segment of the logical address space is defined as a Far segment, such that only a jump to a logical address in this segment leads to a change of the memory area by using the second jump instruction.