Soft Errors Handling in Eeprom Devices

1. A method of improving data retention in a nonvolatile writable memory having a first reference level and a second reference level, the nonvolatile writable memory having a plurality of memory cells, each of the memory cells being in an first state when storing a charge below the first reference level, and each of the memory cells being in a second state when storing a charge above the second reference level, the method comprising: writing into each of a set of the plurality of memory cells a respective data value, wherein the respective data values are one of the first and second states; identifying a memory cell of the set having a charge above the first reference level and below the second reference level; and rewriting the respective data value into the memory cell.

2. The memory of claim 1 , further having a third reference level intermediate between the first and second reference levels, wherein the identifying comprises identifying a memory cell of the set having a charge above the third reference level and below the second reference level.

3. The memory of claim 2 , further having a fourth reference level intermediate between the second and third reference levels, wherein the identifying comprises identifying a memory cell of the set having a charge above the third reference level and below the fourth reference level.

4. The memory of claim 1 , wherein the rewriting comprises determining the respective data value to rewrite into the data cell using error correction code.

5. A method of improving data retention in a nonvolatile writable memory having a first reference level and a second reference level, the nonvolatile writable memory having a plurality of memory cells organized into sectors, each of the memory cells being in an first state when storing a charge below the first reference level, and each of the memory cells being in a second state when storing a charge above the second reference level, the method comprising: accessing a first sector of said memory cells each storing a respective data value, wherein the respective data values are one of the first and second states; identifying a second sector of said memory cells having one or more memory cells with a charge above the first reference level and below the second reference level; and rewriting the respective data values stored in the memory cells of the second sector.

6. The memory of claim 5 , wherein said accessing a first sector of said memory cells comprises programming data values into said memory cells of the first sector, wherein the data values are one of the first and second states.

7. The memory of claim 5 , wherein said accessing a first sector of said memory cells comprises reading the data values stored in said memory cells of the first sector, wherein the data values are one of the first and second states.

8. The memory of claim 5 , wherein said second sector is chosen at random prior to said identifying.

9. The memory of claim 5 , wherein a memory cells of said first sector shares a common bit line with a memory cell of said second sector.