System and Method for Providing Adaptive Power Supply to System on a Chip

1. A system for adaptively providing a power supply voltage, the system comprising: an input/output subsystem configured to receive a first voltage; an analog subsystem configured to receive a second voltage and coupled to the input/output subsystem; a first digital subsystem configured to receive a third voltage and coupled to the input/output subsystem; a first adaptive power supply configured to receive an input voltage and generate the third voltage; wherein: the first digital subsystem is configured to receive a clock signal associated with a clock frequency; the first adaptive power supply is further configured to adjust the third voltage based on at least information associated with a comparison of a first frequency and the clock frequency.

2. The system of claim 1 wherein: the first digital subsystem includes a plurality of digital blocks; the plurality of digital blocks are associated with a plurality of critical paths respectively; the plurality of critical paths are related to a plurality of signal time delays respectively; the plurality of signal time delays are substantially equal.

3. The system of claim 1 , and further comprising: a second digital subsystem coupled to the input/output subsystem; a first digital connection configured to carry a first plurality of digital signals between the first digital subsystem and the second digital subsystem; a second digital connection configured to carry a second plurality of digital signals between the second digital subsystem and the analog subsystem.

4. The system of claim 3 , and further comprising: a third digital connection configured to carry a third plurality of digital signals between the first digital subsystem and the input/output subsystem; a fourth digital connection configured to carry a fourth plurality of digital signals between the analog subsystem and the input/output subsystem.

5. The system of claim 4 wherein each of the first digital connection, the second digital connection, the third digital connection, and the fourth digital connection comprises one or more level shifters.

6. The system of claim 1 wherein the third voltage is adjusted if the first frequency and the clock frequency are not equal.

7. The system of claim 1 wherein the first digital subsystem is configured to adjust the clock frequency based on at least information associated with a workload of the first digital subsystem.

8. The system of claim 1 wherein: the first digital subsystem includes a first signal path associated with a first time delay; the first adaptive power supply comprises: a frequency comparator configured to receive a first signal associated with the first frequency and a first period, to receive a second signal associated with the clock frequency, and to generate a third signal if the first frequency and the clock frequency are not equal; a voltage regulator coupled to the frequency comparator and configured to generate the third voltage based on at least information associated with the third signal; wherein: the first period is equal to or longer than the first time delay.

9. The system of claim 8 wherein the second signal and the clock signal are the same.

10. The system of claim 8 wherein the first adaptive power supply further comprises an oscillator configured to receive the third voltage and generate the first signal associated with the first frequency and the first period.

11. The system of claim 10 wherein: the oscillator includes a second signal path associated with a second time delay; the second time delay is substantially equal to the first period.

12. The system of claim 8 wherein: the first digital subsystem further includes other signal paths associated with corresponding other time delays; each of the other time delays is shorter than the first time delay.