Multithread Processor

1. A processor comprising an issue instruction multiplexer which decodes an instruction supplied to said issue instruction multiplexer, wherein: said instruction has instruction issue information for the next and subsequent operating cycles after the operating cycle in which said instruction was issued; said instruction has information showing the position of an operating cycle in which said instruction can be issued; and said instruction issue information is information generated on the first occasion of said instruction, or on the immediately preceding occasion it was executed.

2. The processor according to claim 1 , further comprising an instruction cache which temporarily holds said instruction and an instruction issue information buffer which temporarily holds said instruction issue information, and said instruction issue information is read from said instruction issue information buffer together with said instruction read from said instruction information storage part.

3. The processor according to claim 1 , wherein said instruction has a priority, said issue instruction multiplexer issues a high priority instruction to said operating cycle based on said instruction issue information, and issues a low priority instruction to a different operating cycle from said operating cycle.

4. The processor according to claim 3 , comprising said issue instruction multiplexer with an issue possibility judgment circuit which judges whether or not to issue said instruction, and said issue possibility judgment circuit is inactivated when said high priority instruction can be issued.

5. A processor which executes plural threads simultaneously or by time division without save and restore of a processor state; said plural threads have a priority; and when an instruction flow in a 1st priority thread is executed for the first time, the position of an operating cycle at which an instruction in said instruction flow can be issued is stored, and in the execution of a second and subsequent instruction flows, a 2nd priority thread is executed in a different operating cycle from said operating cycle, wherein said instruction has issue information generated on the first occasion of said instruction, or on the immediately preceding occasion it was executed.