Method for Creation of Secure Simulation Models

1. A method of producing a simulation model of an electronic design, the method comprising: receiving a non-obfuscated version of the electronic design suitable for direct compilation into a practical hardware implementation of the electronic design; identifying a region of said electronic design into which a type of obfuscation may be added; adding obfuscation circuitry to said electronic design to produce an obfuscated version of the electronic design, wherein said obfuscation circuitry prevents practical implementation of the electronic design on a target hardware device; creating a simulation model using said obfuscated version of said electronic design, said simulation model being suitable for producing accurate hardware simulation results in a simulator but not being suitable to be directly compiled to produce a practical hardware implementation of the electronic design; storing said simulation model in a computer system; and wherein adding the obfuscation circuitry comprises: at a first location, adding circuitry for entangling multiple input signals to thereby spread out the input signals; and at a second location, adding circuitry for detangling an output signal resulting from the circuitry for entangling.

2. A method as recited in claim 1 , wherein the non-obfuscated version of the electronic design is provided in an HDL source format and said creating a simulation model includes using said obfuscated version of said electronic design as said simulation model.

3. A method as recited in claim 1 , wherein the electronic design is a reusable functional logic block.

4. A method as recited in claim 1 , wherein adding obfuscation circuitry includes: identifying a region for introduction of obfuscation circuitry in the non-obfuscated version of the electronic design; choosing a type of obfuscation circuitry for insertion; and inserting the chosen type of obfuscation circuitry into the identified region, thereby creating an obfuscated region.

5. A method as recited in claim 4 , wherein identifying a region for introduction of obfuscation circuitry includes identifying in the non-obfuscated version of the electronic design logic of a type that is not removed by a synthesizer.

6. A method as recited in claim 5 , wherein the type of logic that is not removed by a synthesizer includes one or more flip-flops.

7. A method as recited in claim 1 , further comprising: optimizing the obfuscated version of the electronic design by merging the obfuscation circuitry with non-obfuscated functional circuitry of said obfuscated version.

8. A method as recited in claim 1 , wherein the obfuscation circuitry increases the size of the electronic design without changing its function or slows the speed of the electronic design without changing its function.

9. A method as recited in claim 1 , wherein adding obfuscation circuitry comprises: at a first location, adding circuitry for scrambling an input signal by spreading out the input signal in time; and at a second location, adding circuitry for de-scrambling an output signal resulting from the circuitry for scrambling.

10. A method as recited in claim 1 , wherein the obfuscation circuitry includes an XOR tree.

11. A method as recited in claim 1 , wherein adding obfuscation circuitry is performed automatically without user intervention.

12. An apparatus for producing a simulation model of an electronic design, the apparatus comprising: one or more processors; memory; a design entry tool that allows a developer to input a non-obfuscated version of said electronic design; an obfuscation module for identifying a region of said electronic design and adding obfuscation circuitry to said non-obfuscated version of the electronic design to produce an obfuscated version of the electronic design from which the simulation model can be created, wherein said obfuscation circuitry prevents practical implementation of the electronic design on a target hardware device, said obfuscation module creating said simulation model, said simulation model being suitable for producing accurate hardware simulation results in a simulator but not being suitable to be directly compiled to produce a practical hardware implementation of the electronic design; and wherein the obfuscation circuitry comprises: at a first location, an entangler having circuitry for entangling multiple input signals to thereby spread out the input signals; and at a second location, a detangler having circuitry for detangling an output signal resulting from the circuitry for entangling.

13. An apparatus as recited in claim 12 , wherein the non-obfuscated version of the electronic design is in an HDL source format, said simulation model being said obfuscated version of said electronic design.

14. An apparatus as recited in claim 12 , wherein the electronic design is a reusable functional logic block.

15. An apparatus as recited in claim 12 , wherein the obfuscation module comprises: a scanning module for identifying a region for introduction of obfuscation circuitry in the non-obfuscated version of the electronic design; a selection module for choosing a type of obfuscation circuitry for insertion; and an insertion module for inserting the chosen type of obfuscation circuitry into the identified region, thereby creating an obfuscated region.

16. An apparatus as recited in claim 15 , wherein the scanning module for identifying a region for introduction of obfuscation circuitry includes identifying in the non-obfuscated version of the electronic design logic of a type that is not removed by a synthesizer.

17. An apparatus as recited in claim 16 , wherein the type of logic that is not removed by a synthesizer includes one or more flip-flops.

18. An apparatus as recited in claim 13 , further comprising: an optimizer for optimizing the obfuscated version of the electronic design by merging the obfuscation circuitry with non-obfuscated functional circuitry of said obfuscated version.

19. An apparatus as recited in claim 12 , wherein the obfuscation circuitry increases the size of the electronic design without changing its function or slows the speed of the electronic design without changing its function.

20. An apparatus as recited in claim 12 , wherein the obfuscation circuitry comprises: at a first location, a scrambler having circuitry for scrambling an input signal by spreading out the input signal in time; and at a second location, a descrambler having circuitry for de-scrambling an output signal resulting from the circuitry for scrambling.

21. An apparatus as recited in claim 12 , wherein the obfuscation circuitry includes an XOR tree.

22. An apparatus as recited in claim 15 , wherein the scanning module, the selection module, and the insertion module are configured to operate automatically without user intervention.

23. A computer program product comprising a tangible computer readable storage medium on which is provided program instructions for producing a simulation model of an electronic design, the program instructions comprising: instructions for receiving a non-obfuscated version of the electronic design suitable for direct compilation into a practical hardware implementation of the electronic design; instructions for identifying a region of said electronic design into which a type of obfuscation may be added; instructions for adding obfuscation circuitry to said electronic design to produce an obfuscated version of the electronic design, wherein said obfuscation circuitry prevents practical implementation of the electronic design on a target hardware device; instructions for creating a simulation model using said obfuscated version of said electronic design, said simulation model being suitable for producing accurate hardware simulation results in a simulator but not being suitable to be directly compiled to produce a practical hardware implementation of the electronic design; and wherein the instructions for adding obfuscation circuitry comprise: instructions for adding circuitry at a first location to entangle multiple input signals to thereby spread out the input signals; and instructions for adding circuitry at a second location to detangle an output signal resulting from the circuitry to entangle.

24. A computer program product as recited in claim 23 , wherein the non-obfuscated version of the electronic design is provided in an HDL source format and said creating a simulation model includes using said obfuscated version of said electronic design as said simulation model.

25. A computer program product as recited in claim 23 , wherein the electronic design is a reusable functional logic block.

26. A computer program product as recited in claim 23 , wherein the instructions for adding obfuscation circuitry comprises: instructions for identifying a region for introduction of obfuscation circuitry in the non-obfuscated version of the electronic design; instructions for choosing a type of obfuscation circuitry for insertion; and instructions for inserting the chosen type of obfuscation circuitry into the identified region, thereby creating an obfuscated region.

27. A computer program product as recited in claim 26 , wherein the instructions for identifying a region for introduction of obfuscation circuitry comprises identifying in the non-obfuscated version of the electronic design logic of a type that is not removed by a synthesizer.

28. A computer program product as recited in claim 27 , wherein the type of logic that is not removed by a synthesizer includes one or more flip-flops.

29. A computer program product as recited in claim 26 , further comprising: instructions for optimizing the obfuscated version of the electronic design by merging the obfuscation circuitry with non-obfuscated functional circuitry of said obfuscated version.

30. A computer program product as recited in claim 23 , wherein the obfuscation circuitry increases the size of the electronic design without changing its function and/or slows the speed of the electronic design without changing its function.

31. A computer program product as recited in claim 23 , wherein the instructions for adding obfuscation circuitry comprise: instructions for adding circuitry at a first location to scramble an input signal by spreading out the input signal in time; and instructions for adding circuitry at a second location to de-scrambling an output signal resulting from the circuitry to scramble.

32. A computer program product as recited in claim 23 , wherein the obfuscation circuitry includes an a XOR tree.

33. A computer program product as recited in claim 26 , wherein the operations of identifying, choosing, and inserting can be done automatically without user intervention.

34. A method of producing a simulation model of an intellectual property core, wherein the simulation model produces a hardware simulation result but cannot be directly compiled to produce a practical hardware implementation of the IP core, the method comprising: (a) receiving a non-obfuscated version of the IP core in a native HDL format or in a partially compiled HDL format; (b) identifying a region of the non-obfuscated IP core where one or more flip-flops are located; (c) inserting entangler circuitry upstream from the region and inserting complementary detangler circuitry downstream from the region; (d) inserting scrambler circuitry upstream from the region and inserting complementary descrambler circuitry downstream from the region; (e) optimizing the IP core after the insertions of (c) and (d); and (f) producing a simulation model using said optimized IP core that includes said inserted entangler and inserted scrambler circuitry.

35. A method as recited in claim 8 , wherein the obfuscation circuitry increases the area of the electronic design or reduces the speed of a critical path of the electronic design.

36. An apparatus as recited in claim 19 , wherein the obfuscation circuitry increases the area of the electronic design or reduces the speed of a critical path of the electronic design.

37. A computer program product as recited in claim 30 , wherein the obfuscation circuitry increases the area of the electronic design or reduces the speed of a critical path of the electronic design.

38. A method as recited in claim 34 , wherein said entangler and scrambler circuitry increases the area of said functional logic block and reduces the speed of a critical path of said functional logic block.

39. A method as recited in claim 1 wherein said simulation model is cycle accurate and bit accurate.

40. An apparatus as recited in claim 12 wherein said simulation model is cycle accurate and bit accurate.

41. A computer program product as recited in claim 23 wherein said simulation model is cycle accurate and bit accurate.

42. A method as recited in claim 34 further comprising: producing a simulation model using said optimized intellectual property core, wherein said simulation model is cycle accurate and bit accurate.

43. A method as recited in claim 34 further comprising: producing a simulation model using said optimized intellectual property core, wherein said simulation model is cycle accurate and bit accurate.

44. A method as recited in claim 3 wherein said functional logic block is an intellectual property core.

45. An apparatus as recited in claim 14 wherein said functional logic block is an intellectual property core.

46. A computer program product as recited in claim 25 wherein said functional logic block is an intellectual property core.

47. A method as recited in claim 1 , wherein the non-obfuscated version of the electronic design is provided in a partially compiled format, and wherein said creating a simulation model includes using a translation utility to convert said obfuscated version of said electronic design into said simulation model having a standard format usable by a variety of simulators.

48. An apparatus as recited in claim 12 , wherein the non-obfuscated version of the electronic design is provided in a partially compiled format, said apparatus further comprising: a model writer module that converts said obfuscated version of said electronic design into said simulation model having a standard format usable by a variety of simulators.

49. A computer program product as recited in claim 23 , wherein the non-obfuscated version of the electronic design is provided in a partially compiled format, and wherein said creating a simulation model includes using a translation utility to convert said obfuscated version of said electronic design into said simulation model having a standard format usable by a variety of simulators.