Apparatus and Method of Analyzing Packetized Data Spanning Over Multiple Clock Cycles

1. Apparatus for processing packetized data spanning multiple clock cycles, comprising: a counter for counting cycles of a clock signal, said counter being responsive to said clock signal, to a Data Valid signal indicative of the presence of valid data, and to an SOP signal indicative of a start of a packet, said counter incrementing its clock cycle count in response to each of said clock cycles when said Data Valid signal is present, said counter having a range of counts at least equal to a length of said packet; a first comparator, for comparing a present clock cycle count to one of a plurality of reference clock cycle count values and producing a first enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said first comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a second comparator, for comparing said clock cycle count to one of a plurality of reference clock cycle count values and producing a second enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said second comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a first word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said first enable signal; a second word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said second enable signal; and an output circuit for providing an indication of whether said digital word comparisons produced a determination of equality at each clock cycle corresponding to a reference clock cycle count value.

2. The apparatus of claim 1 , wherein: said apparatus includes more than two comparators and said reference clock cycle count value of said first comparator is non-contiguous with said reference clock cycle count value of any other of said comparators.

3. The apparatus of claim 1 , wherein said reference clock cycle count value of said first and second comparators is the same value.

4. The apparatus of claim 1 , wherein said output circuit comprises: a multiplexer coupled to receive said output determination signals of said first and second word recognizers; and a latch coupled to said multiplexer for storing the determination signal.

5. The apparatus of claim 1 , wherein said word recognizers are capable of enabling individual bits of said digital words for comparison, and at least one bit of said presently received digital word and said reference digital word is enabled for comparison.

6. The apparatus of claim 1 , wherein said indication of favorable digital word comparisons remains False unless said digital word comparisons produced a determination of equality at all clock cycles corresponding to a reference clock cycle count value.

7. The apparatus of claim 1 , wherein said indication of favorable digital word comparisons remains TRUE unless said digital word comparisons produced a determination of non-equality at any of said clock cycles corresponding to a reference clock cycle count value.

8. Apparatus for processing packetized data spanning multiple clock cycles, comprising: a counter for counting cycles of a clock signal, said counter being responsive to said clock signal, to a Data Valid signal indicative of the presence of valid data, and to an SOP signal indicative of a start of a packet, said counter incrementing its clock cycle count in response to each of said clock cycles when said Data Valid signal is present, said counter having a range of counts equal to a length of said packet; a first comparator, for comparing a present clock cycle count to one of a plurality of reference clock cycle count values and producing a first enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said first comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a second comparator, for comparing said clock cycle count to one of a plurality of reference clock cycle count values and producing a second enable signal in response to a favorable determination, said favorable determination being a determination that said present clock cycle count is equal to said reference clock cycle count value of said second comparator, and wherein each of said reference clock cycle count values can be equal to any count value within said range of counts of said counter; a word recognizer, for comparing a presently received digital word to a reference digital word and producing a determination of equality or non-equality in response to said first enable signal, thereafter said word recognizer being programmed with a second reference digital word for comparing a further received digital word to said second reference digital word and producing a determination of equality or non-equality in response to said second enable signal; and an output circuit for providing an indication of whether said digital word comparisons produced a determination of equality at each clock cycle corresponding to a reference clock cycle count value.

9. The apparatus of claim 8 , further comprising: a plurality of enable value registers and a respective plurality of compare value registers each having an output coupled to said word recognizer; each of said comparators respectively associated with an enable value register and a compare value register; a select logic device for enabling transfer of respective enable and compare values to said word recognizer in response to said comparator having produced said favorable determination.

10. The apparatus of claim 8 , wherein said word recognizers are capable of enabling individual bits of said digital words for comparison, and at least one bit of said presently received digital word and said reference digital word is enabled for comparison.

11. The apparatus of claim 9 , wherein: said plurality of compare value registers each provides a predetermined compare reference digital word value; and said plurality of enable value registers respectively specify said individual bits used to perform comparisons to said reference digital word values, said enabled digital bits forming predetermined data channels.

12. The apparatus of claim 8 , wherein: said output circuit comprises a multiplexer coupled to receive said output determination signals of said first and second word recognizers; and a latch coupled to said multiplexer for storing the determination signal.

13. The apparatus of claim 8 , wherein said indication of favorable digital word comparisons remains FALSE unless said digital word comparisons produced a determination of equality at all clock cycles corresponding to a reference clock cycle count value in which case said indication becomes TRUE.

14. The apparatus of claim 8 , wherein said indication of favorable digital word comparisons remains TRUE unless said digital word comparisons produced a determination of non-equality at any of said clock cycles corresponding to a reference clock cycle count value.

15. The apparatus of claim 13 wherein said apparatus is a logic analyzer and said logic analyzer is triggered upon detection of said TRUE indication.

16. The apparatus of claim 14 wherein said apparatus is a logic analyzer and said logic analyzer is triggered when said indication is TRUE upon detection of an End of Packet signal.

17. Method for processing packetized data spanning multiple clock cycles, comprising: counting cycles of a clock in a counter, said counter counting from a start of packet (SOP) signal only in response to a Data Valid signal indicative of the presence of valid data, said counter having a range equal to a length of a packet; comparing, at each of a plurality of comparators, a present clock cycle count from the counter to a reference clock cycle value and producing a respective enable signal at each of said comparators in response to a determination that said present cycle count equals its respective reference clock cycle value; enabling at least one word recognizer of a respective plurality of word recognizers in response to said respective enable signal; comparing, at at least one word recognizer, a presently received digital word from the packetized data to a reference digital word; providing, at an output of an enabled word recognizer, an indication of a favorable word comparison; and providing, at an output, a TRUE indication when said digital word comparisons produced a determination of equality at each clock cycle count from the counter corresponding to the reference clock cycle count value.

18. The method of claim 17 , further comprising setting each of said plurality of comparators with a different predetermined reference clock cycle count value.

19. The method of claim 17 , further comprising setting at least two of said plurality of comparators with the same predetermined reference clock cycle count value.

20. The method of claim 17 further comprising triggering a logic analyzer in response to said TRUE indication.