Output Buffer Circuit with De-Emphasis Function

1. An output buffer circuit comprising: a first output buffer for data; and a second output buffer; said first output buffer and said second output buffer having respective output ends connected to an output terminal of said output buffer circuit; said output buffer circuit receiving a data signal to be output and performing a de-emphasis function in which the amplitude of an output signal emphasized at a transition time when the logic of the output signal is changed, is attenuated when the logic of the output signal following the transition remains unchanged, said output buffer circuit further comprising a circuit for performing switching control in such a way that, when de-emphasis is disabled, said second output buffer is made to operate as an output buffer for data, and when de-emphasis is enabled, said second output buffer is made to operate as an output buffer for de-emphasis.

2. A semiconductor device having said output buffer circuit as set fourth in claim 1 .

3. A serial interface circuit having said output buffer circuit as set fourth in claim 1 .

4. An output buffer circuit comprising: a first output buffer for data, receiving a data signal and outputting the data signal from an output terminal thereof; a second output buffer having an output end connected to said output terminal and a selection circuit, receiving a control signal indicating whether de-emphasis is enabled or disabled, for performing switching control in such a way that, when the control signal indicates that de-emphasis is disabled, said data signal is supplied to an input end of said second output buffer to make said second output buffer operate as a buffer for data; and when the control signal indicates that de-emphasis is enabled, emphasis data obtained on delaying said data signal is supplied to the input end of said second output buffer to make said second output buffer operate as a buffer for de-emphasis.

5. The output buffer circuit according to claim 4 , wherein the data signal comprises a differential signal; said output buffer circuit further comprises a delay circuit differentially receiving the data signal for delaying the data signal to output differentially the delayed signal; said first output buffer comprises: a first pre-buffer composed of a differential circuit; and a first main buffer composed of a differential circuit that receives an output signal from said first pre-buffer; said second output buffer comprises a second main buffer composed of a differential circuit; a non-inverting output and an inverting output of the differential output of said first main buffer and an inverting output and a non-inverting output of the differential output of said second main buffer are connected in common respectively and are connected to a non-inverting terminal and an inverting terminal of a differential output terminal pair; and wherein said selection circuit receives a differential signal obtained on inverting the data signal, and a differential signal obtained on delaying the data signal by said delay circuit; said selection circuit, when the control signal indicates that de-emphasis is enabled, supplying the signal obtained on delaying the data signal by said delay circuit, to the input end of said second main buffer; while said selection circuit, when the control signal indicates that de-emphasis is disabled, supplying the signal obtained on inverting the data signal to the input end of said second main buffer to make said first and second main buffers operate as an adder and to make said second output buffer operate as a main-data output buffer.

6. The output buffer circuit according to claim 5 , further comprising: a third buffer composed of a differential circuit; a non-inverting output and an inverting output of the differential output of said first main buffer and an inverting output and a non-inverting output of the differential output of said third buffer being connected in common respectively; and a second selection circuit receiving the differential signal obtained on inverting the data signal, and the differential signal obtained on delaying the data signal by said delay circuit; said second selection circuit, when a second control signal received indicates that de-emphasis is enabled, supplying the signal obtained on delaying the data signal by said delay circuit, to an input end of said third buffer; while said second selection circuit, when the second control signal received indicates that de-emphasis is disabled, supplying the signal obtained on inverting the data signal to the input end of said third buffer.

7. An output buffer circuit comprising: an inverter circuit receiving a data signal to output an inverted signal of the a data signal; a first inverting-type output buffer receiving the output signal from said inverter circuit as an input and outputting the inverted signal from an output terminal thereof; a delay circuit delaying the data signal; a selection circuit receiving an output signal of said delay circuit and the output signal of said inverter circuit and receiving a control signal indicating whether de-emphasis is to be enabled or disabled, for selecting the output signal of said inverter circuit for output, when the control signal indicates that de-emphasis is to be disabled, and selecting the output signal of said delay circuit for output, when the control signal indicates that de-emphasis is to be enabled; and a second inverting-type output buffer receiving the output of said selection circuit as an input and having an output connected in common with the output of said first inverting-type output buffer.

8. The output buffer circuit according to claim 7 , further comprising: a second selection circuit receiving the output signal of said delay circuit and the output signal of said inverter circuit and selecting one of the output signals received based on a second control signal received; and a third inverting-type output buffer receiving the output signal of said second selection circuit as an input and having an output connected in common with the output of said first inverting-type output buffer.