Legal claims defining the scope of protection, as filed with the USPTO.
1. A programmable processor, comprising: a memory lock signal generator outputting a memory lock signal, the memory lock signal indicating whether a requesting entity has authority to access requested data stored in a memory; and a memory access controller receiving a request for the requested data and the memory lock signal, the memory access controller outputting a response to the requesting entity in response to the request based on the memory lock signal.
2. The programmable processor of claim 1 , wherein the memory lock signal generator indicates that the requesting entity does not have authority to access the requested data if the requesting entity is not a central processing unit.
3. The programmable processor of claim 1 , wherein the memory access controller outputs the response to the requesting entity as a default value if the memory lock signal indicates that the requesting entity does not have authority to access the requested data.
4. The programmable processor of claim 1 , wherein the requested data is included within a location reserved for protected data.
5. The programmable processor of claim 4 , wherein the protected data includes operation code.
6. The programmable processor of claim 1 , wherein the memory includes a first memory portion for storing the protected data and a second memory portion for storing unprotected data.
7. The programmable processor of claim 6 , wherein the memory access controller outputs the requested data as the response if the requested data is stored in the second memory portion.
8. The programmable processor of claim 1 , wherein the memory lock signal generator determines whether the requesting entity is a central processing unit based on a status of an operation code fetch signal of the central processing unit.
9. The programmable processor of claim 8 , wherein the memory lock signal generator generates the memory lock signal indicating that the central processing unit has authority to access the requested data.
10. The programmable process of claim 9 , wherein the memory access controller transmits the requested data to the central processing unit as the response.
11. The programmable processor of claim 1 , wherein the programmable processor is included within a system-on-chip (SOC).
12. The programmable processor of claim 1 , wherein the memory lock signal generator outputs the memory lock signal indicating that the requesting entity has authority to access the requested data if the request is associated with a debugging operation, the debugging operation authorized by a central processing unit.
13. The programmable processor of claim 12 , wherein the memory access controller outputs the response to the requesting entity as a default value if the debugging operation is not authorized by the central processing unit.
14. The programmable processor of claim 12 , wherein the memory lock signal generator includes: a debugging determination unit outputting a debugging execution signal indicating whether a debugging operation is being performed; an execution device identification unit outputting an execution device identification signal indicating whether the central processing unit authorizes the debugging operation; and a logic determination unit determining a status of the memory lock signal based on the debugging execution signal and the execution device identification signal.
15. The programmable processor of claim 14 , wherein the logic determination unit is an AND gate performing an AND operation of the debugging execution signal and the execution device identification signal to output the memory lock signal.
16. The programmable processor of claim 14 , wherein the execution device identification unit includes a register to determine whether the debugging is performed by the central processing unit based on information received from the central processing unit.
17. The programmable processor of claim 12 , wherein the debugging operation is carried out by a Joint Test Action Group (JTAG) device.
18. A method for protecting data stored in a memory of a programmable processor, comprising: receiving a request, from a requesting entity, to access requested data stored in the memory; determining information associated with the requesting entity; and selectively outputting a response to the received request based on a security level of a location of the requested data within the memory and the determined information.
19. The method of claim 18 , wherein selectively outputting the response includes: outputting a default value if the requested data is stored in a portion of the memory reserved for protected data and the determined information indicates that the requesting entity is not authorized to receive the requested data; and outputting the requested data if the requested data is not stored in a portion of the memory reserved for protected data.
20. The method of claim 19 , wherein the determined information indicates that the requesting entity is not authorized to receive the requested data if the requesting entity is not a central processing unit of the programmable processor.
21. The method of claim 18 , wherein the default value is one of a first logic level and a second logic level.
22. The method of claim 21 , wherein the first logic level is a higher logic level and the second logic level is a lower logic level.
23. The method of claim 18 , wherein the memory includes a first memory portion for storing protected data and a second memory portion for storing unprotected data.
24. The method of claim 18 , wherein determining information associated with the requesting entity determines whether the requesting entity is a central processing unit based on a status of an operation code fetch signal received from the central processing unit.
25. The method of claim 24 , further comprising: transmitting the requested data to the central processing unit if the operation code fetch signal is enabled.
26. The method of claim 18 , wherein determining information associated with the requesting entity includes determining whether the requesting entity is performing a debugging operation.
27. The method of claim 26 , further comprising: determining whether standard data is input to a register; and outputting a default value as the response to the request for the requested data if the requesting entity is performing a debugging operation and the standard data is not input to the register; and outputting the requested data as the response to the request for the requested data if the standard data is input to the register.
28. The method of claim 27 , wherein the requested data is output to a central processing unit.
29. The method of claim 26 , wherein the requesting entity is a debugging tool.
30. The method of claim 29 , wherein the debugging tool is a Joint Test Action Group (JTAG) device.
31. The method of claim 18 , further comprising: transmitting the requested data to the requesting entity if the requested data is associated with a lower security level irrespective of the determined information.
32. A method for protecting data stored in a memory of a programmable processor, comprising: receiving a memory lock signal indicating whether a requesting entity has authority to access requested data stored in a memory; receiving a request for the requested data from the requesting entity; and selectively outputting one of the requested data and a default value other than the requested data to the requesting entity based on the memory lock signal.
33. A method for protecting data stored in a memory of the programmable processor of claim 1 .
Unknown
March 31, 2009
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