7516109

Automatically Deriving Logical, Arithmetic and Timing Dependencies

PublishedApril 7, 2009
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
15 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A computer-implemented method for verifying the behavior of a digital system, said method comprising, receiving a constraint graph with directed arcs, each said directed arc being labeled with a Boolean formula, said constraint graph having at least one accepted path, each accepted path in said constraint graph being labeled with a sequence of Boolean formulas describing a disallowed pattern of behavior of said digital system; receiving a list of non-visible signals; starting with said constraint graph, performing for each non-visible signal in the list of non-visible signals: (a) performing either (a1) all possible resolutions of equal-length directed paths within the constraint graph of said non-visible signal or (a2) selected resolutions of equal-length directed paths within the constraint graph of said non-visible signal; (b) deleting all arcs in a resulting constraint graph that are labeled with a Boolean formula that mentions said non-visible signal; (c) deleting all arcs in the resulting constraint graph that are no longer on a directed path from an original initial node of the constraint graph to an original terminal node of the constraint graph; supplying the resulting constraint graph to a constraint-based simulator; supplying input values to said constraint-based simulator; using said input values and constraints accepted by said constraint graph to calculate output values; responding to a user query about a particular output value by determining the input values and the constraint, or constraints, used to calculate said output value; and supplying to the user said input values and said constraint, or constraints.

2

2. A computer-implemented method for verifying the behavior of a digital system, comprising: a constraint-based inference engine receiving logical/temporal/data dependencies describing the behavior of a digital system; deriving new logical/temporal/data dependencies describing the input/output behavior of the digital system; and wherein said logical/temporal/data dependencies received by and derived by said inference engine are in the form of a directed graph in which each arc is labeled with a Boolean formula.

3

3. The method of claim 2 wherein said method labels each node of said received directed graph, or a copy thereof, with a data structure.

4

4. The method of claim 3 wherein a new directed graph with labeled nodes and arcs is obtained from an existing directed graph with labeled nodes and arcs by resolution comprising the following steps: (a) deriving from equal-length directed paths in said existing directed graph a new directed path that is the same length as said equal-length paths such that the Boolean formula labeling the i'th arc of this new path is obtained from the Boolean formulas labeling the i'th arcs of said equal-length paths and the data structure labeling the i'th node of this new path is obtained from the data structures labeling the i'th nodes of said equal-length paths; (b) adding the nodes and arcs of the derived path to the existing directed graph.

5

5. The computer-implemented method of claim 4 wherein said resolution is via a selected signal S in a selected position k of said equal-length paths.

6

6. The computer-implemented method of claim 5 , comprising the following steps for a system signal S: (6a) performing selected resolutions via said signal S; (6b) deleting all arcs labeled with a Boolean formula in which signal S appears; (6c) deleting all nodes and arcs not lying on a directed path from an initial node of the original directed graph prior to Steps (6a) and (6b) to a terminal node of the original directed graph prior to Steps (6a) and (6b).

7

7. The computer-implemented method of claim 6 in which the steps (6a), (6b), and (6c) are repeated for each non-input, non-output signal S.

8

8. The computer-implemented method of claim 4 in which said method labels each said node with a set of sets of node names of the original received directed graph.

9

9. The computer-implemented method of claim 4 wherein said method labels each said node with an ordered pairs <aft, fore> where aft and fore are each a set of sets of node names of the original received directed graph.

10

10. The computer-implemented method of claim 9 wherein said method labels the nodes of said received constraint graph, or a copy thereof, as follows: (a) each initial node is labeled with the ordered pair <{ }, {{ }}>; (b) each internal node N is labeled with the ordered pair <{{N}}, {{N}}>; (c) each terminal node is labeled with the ordered pair <{{ }}, { }>.

11

11. A computer-implemented method comprising: a constraint-based simulator receiving (a) logical/temporal/data dependencies describing the input/output behavior of a digital system, (b) values for various input signals at various simulation times; and said constraint-based simulator determining values for various output signals at various simulation times using said logical/temporal/data dependencies.

12

12. The computer-implemented method of claim 11 wherein said received logical/temporal/data dependencies are in the form of a constraint graph.

13

13. The computer-implemented method of claim 12 wherein said values for various input signals and said values for various output signals are displayed in a two-dimensional tabular form wherein signals are associated with one dimension and simulation times are associated with the other dimension.

14

14. A computer-implemented method for simulating the behavior of a digital system comprising: receiving a constraint graph with directed arcs in which each said directed arc is labeled with a Boolean formula, said constraint graph having at least one accepted path, each accepted path in said constraint graph being labeled with a sequence of Boolean formulas describing a disallowed pattern of behavior of a digita 1 system; receiving values for selected input signals; using said input values and constraints accepted by said constraint graph to calculate values for selected output signals at various simulation times.

15

15. The computer-implemented method of claim 14 , further comprising: responding to a user query about a particular output value by determining the input values and the constraint, or constraints, used to calculate said output value; supplying to the user said input values and said constraint, or constraints, in at least one of several alternate formats.

Patent Metadata

Filing Date

Unknown

Publication Date

April 7, 2009

Inventors

Frederick C. Furtek

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Cite as: Patentable. “AUTOMATICALLY DERIVING LOGICAL, ARITHMETIC AND TIMING DEPENDENCIES” (7516109). https://patentable.app/patents/7516109

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