Technique for Providing Service Processor Access to Control and Status Registers of a Module

1. A computer system, comprising: a host module (HM); and a plurality of client modules (CMs) in communication with the HM and each including one or more associated registers, wherein each of the CMs is separately addressable and at least one of the CMs operates at a different clock frequency than the remaining CMs and includes a clock synchronizer, and wherein the clock synchronizer provides a clock enable signal to facilitate reading of or writing to the associated registers of the at least one of the CMs by the HM; and a control and status register (CSR) bus coupling the HM to the CMs, wherein the CSR bus includes separate data-in lines coupling the HM to each of the CMs and a common data-out line coupling the HM to all of the CMs and the HM receives data from an addressed one of the CMs on an associated one of the data-in lines and provides data to the CMs on the data-out line, and wherein the one or more associated registers each include at least one control register and at least one status register.

2. The system of claim 1 , wherein a service processor (SP) in communication with the HM provides a message to the HM to initiate a read of or a write to the registers of one of the CMs.

3. The system of claim 1 , wherein each of the CMs is integrated within a different functional unit.

4. The system of claim 3 , wherein the functional unit is one of a memory control unit (MCU) or a system interface unit (SIU).

5. The system of claim 1 , wherein the CSR bus further comprises a common shift control line, a common read control line and a common write control line coupling the HM to the CMs, and wherein when the HM asserts a read signal on the read control line an addressed one of the CMs provides data to the HM on an associated one of the data-in lines responsive to the clock enable signal when the HM asserts a shift signal on the shift control line.

6. The system of claim 1 , wherein the CSR bus further comprises a common shift control line, a common read control line and a common write control line coupling the HM to the CMs, and wherein when the HM asserts a shift signal on the shift control line all of the CMs store, at least temporarily, data and an address provided, on the data-out line, from the HM responsive to the clock enable signal.

7. The system of claim 6 , wherein each of the CMs compare the address provided by the HM with an associated address and the CM whose associated address matches the address provided by the CM stores the data in the one or more associated registers responsive to a write signal provided by the HM on the write control line.

8. The system of claim 1 , wherein the system is embodied as one or more design files stored on one or more computer readable storage media.

9. A communication system, comprising: a host module (HM); a plurality of client modules (CMs) each including one or more associated registers and a clock synchronizer, wherein each of the CMs is separately addressable and at least one of the CMs operates at a different clock frequency than the remaining CMs, and wherein the clock synchronizer provides a local clock enable signal that synchronizes a frequency of an HM clock signal provided by the HM to a local clock signal of the CMs to facilitate reading of or writing to the registers by the HM; and a control and status register (CSR) bus coupling the HM to the CMs, wherein the CSR bus includes separate data-in lines coupling the HM to each of the CMs and a common data-out line coupling the HM to all of the CMs and the HM receives data from an addressed one of the CMs on an associated one of the data-in lines and provides data to the CMs on the data-out line.

10. The system of claim 9 , further comprising: a service processor (SP) in communication with the HM, wherein the SP provides a message to the HM to initiate a read of or a write to the registers of one of the CMs.

11. The system of claim 9 , wherein each of the CMs is integrated within a different functional unit.

12. The system of claim 11 , wherein the functional unit is one of a memory control unit (MCU) or a system interface unit (SIU).

13. The system of claim 9 , wherein the one or more associated registers each include at least one control register and at least one status register.

14. The system of claim 9 , wherein the CSR bus further comprises a common shift control line and a common read control line coupling the HM to the CMs, and wherein when the HM asserts a read signal on the read control line an addressed one of the CMs provides data to the HM on an associated one of the data-in lines responsive to the local clock enable signal when the HM asserts a shift signal on the shift control line.

15. The system of claim 9 , wherein the CSR bus further comprises a common shift control line and a common write control line coupling the HM to the CMs, and wherein when the HM asserts a shift signal on the shift control line all of the CMs store, at least temporarily, data and an address provided, on the data-out line, from the HM responsive to the local clock enable signal.

16. The system of claim 15 , wherein each of the CMs compare the address provided by the HM with an associated address and the CM whose associated address matches the address provided by the HM stores the data in the one or more associated registers responsive to a write signal provided by the HM on the write control line.

17. A method for facilitating communication between a host module (HM) and a plurality of client modules (CMs), comprising: addressing one of a plurality of CMs, wherein each of the CMs include one or more associated registers and each of the CMs is separately addressable, and wherein at least one of the CMs operates at a different clock frequency than the remaining CMs; providing a clock enable signal, by an addressed one of the CMs, to facilitate reading of or writing to the registers of the addressed CM by the HM, wherein the HM is in communication with a service processor (SP); and coupling the HM to the CMs with a control and status register (CSR) bus, wherein the CSR bus includes separate data-in lines that couple the HM to each of the CMs and a common data-out line that couples the HM to all of the CMs.

18. The method of claim 17 , wherein the SP provides a message to the HM to initiate a read of or a write to the registers of one of the CMs.

19. The method of claim 17 , further comprising: receiving data from the registers of an addressed one of the CMs on an associated one of the data-in lines, wherein the registers include at least one control register and at least one status register.

20. The method of claim 17 , further comprising: providing an address to the CMs on the data-out line, wherein the CSR bus further comprises a common shift control line and a common read control line coupling the HM to the CMs; asserting, by the HM, a read signal on the read control line; and responsive to the clock enable signal, providing data from the addressed one of the CMs to the HM on the associated one of the data-in lines when the HM asserts a shift signal on the shift control line.

21. The method of claim 17 , further comprising: providing, from the HM, data and an address to the CMs on the data-out line, wherein the CSR bus further comprises a common shift control line and a common write control line coupling the HM to the CMs, and wherein when the HM asserts a shift signal on the shift control line all of the CMs store, at least temporarily, the provided data and address responsive to the clock enable signal.

22. The method of claim 20 , wherein each of the CMs compare the address provided by the HM with an associated address and the CM whose associated address matches the address provided by the HM stores the data in the one or more associated registers responsive to a write signal provided by the HM on the write control line.