On-The-Fly Reordering of 32-Bit Per Component Texture Images in a Multi-Cycle Data Transfer

1. A graphics processing unit, comprising: a core configured to process texture image data in 32 bit per component format; a graphics module configured to process said texture image data in 16 bits per component format; a core interface coupled to both said core and said graphics module, said core interface further comprising a transpose buffer configurable to receive from said core said texture image data in 32 bit per component format and output to said graphics module said received texture image data in 16 bits per component format; where said core interface is configurable to receive said texture image data at a speed and to transmit said texture image data at half of said speed.

2. The system of claim 1 where said core interface is further configurable to transmit said texture image data at two components per quad per clock cycle.

3. The graphics processing unit of claim 1 where said transpose buffer comprises two memory banks that are coupled to store all of the data.

4. A method for processing data in a system having a texture module optimized to process data in 32 bit per component format and a graphics module optimized to process data in 16 bit per component format, comprising: providing data from said texture module to a transpose buffer in 32 bit per component format at a first speed; storing said received data in 32 bit per component format in a plurality of banks of said transpose buffer; and outputting said received data in 16 bits per component format from said transpose buffer to a graphics module at said first speed.

5. The method of claim 4 wherein said data is provided from said texture module to said transpose buffer at two components per quad per clock cycle.

6. The method of claim 4 wherein said storing said received data in 32 bit per component format further comprises storing said received data in two memory banks that are coupled to store all of the data.

7. The method of claim 6 wherein each of said two memory banks holds one 16-bit half of said received data in 32 bit per component format.

8. The method of claim 4 wherein said first speed is half of the speed at which data is provided from said texture module to said transpose buffer in 16 bit per component format.