Semiconductor Integrated Circuit, Development Support System and Execution History Tracing Method

1. A semiconductor integrated circuit, comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein when the fourth signal is asserted, the memory content of the stack memory is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first and second signals are negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address.

2. A semiconductor integrated circuit, comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when updating the register, the CPU asserts a first signal, and when executing the indirect branch instruction, the CPU asserts a second signal and outputs a branch address relating to the indirect branch instruction; a loop detection circuit for asserting a third signal during an interval from the assertion of the first signal to the assertion of the second signal; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the second signal; and an address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the second and third signals are asserted, the trace packet control section orders the address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein the loop detection circuit asserts the third signal during an interval from the assertion of the fourth signal to the assertion of the second signal, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the second signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address.

3. A semiconductor integrated circuit, comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when executing the indirect branch instruction, the CPU asserts a first signal and outputs a branch address relating to the indirect branch instruction; a first address register for outputting a stored address when the first signal is asserted to store the branch address output from the CPU, a comparator for comparing the branch address output from the first address register and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first signal; and a second address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the first signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the second address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a second signal when a trace is started, wherein when the second signal is asserted, the memory content of the first address register is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the second address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the second signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address.

4. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that in any one of a case where a call instruction is detected in the source program and a case where a code which indicates execution of an interrupt branch is detected in the trace information, the execution history tracing section acquires a return address from the source program to push the acquired return address and acquires a branch address from the trace information to trace the acquired branch address, and when a return instruction is detected in the source program, the execution history tracing section pops the pushed return address to trace the popped return address.

5. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein when the fourth signal is asserted, the memory content of the stack memory is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first and second signals are negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that in any one of a case where a call instruction is detected in the source program and a case where a code which indicates execution of an interrupt branch is detected in the trace information, the execution history tracing section acquires a return address from the source program to push the acquired return address and acquires a branch address from the trace information to trace the acquired branch address, when a return instruction is detected in the source program, the execution history tracing section pops the pushed return address to trace the popped return address, and when a code which indicates start of a trace is detected in the trace information, the execution history tracing section initializes the pushed return address and acquires any one of an execution address and a branch address corresponding to the code from the trace information to trace the acquired address.

6. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when updating the register, the CPU asserts a first signal, and when executing the indirect branch instruction, the CPU asserts a second signal and outputs a branch address relating to the indirect branch instruction: a loop detection circuit for asserting a third signal during an interval from the assertion of the first signal to the assertion of the second signal; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the second signal: and an address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the second and third signals are asserted, the trace packet control section orders the address register to output the address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction accompanied by a branch address is detected in the trace information, the execution history tracing section stores the branch address and traces the branch address, and when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction not accompanied by a branch address is detected in the trace information, the execution history tracing section traces the stored branch address.

7. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when updating the register, the CPU asserts a first signal, and when executing the indirect branch instruction, the CPU asserts a second signal and outputs a branch address relating to the indirect branch instruction; a loop detection circuit for asserting a third signal during an interval from the assertion of the first signal to the assertion of the second signal; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the second signal; and an address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the second and third signals are asserted, the trace packet control section orders the address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein the loop detection circuit asserts the third signal during an interval from the assertion of the fourth signal to the assertion of the second signal, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the second signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction accompanied by a branch address is detected in the trace information, the execution history tracing section stores the branch address and traces the branch address, when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction not accompanied by a branch address is detected in the trace information, the execution history tracing section traces the stored branch address, and when a code which indicates start of a trace is detected in the trace information, the execution history tracing section acquires any one of an execution address and a branch address corresponding to the code from the trace information to trace the acquired address.

8. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when executing the indirect branch instruction, the CPU asserts a first signal and outputs a branch address relating to the indirect branch instruction; a first address register for outputting a stored address when the first signal is asserted to store the branch address output from the CPU, a comparator for comparing the branch address output from the first address register and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first signal; and a second address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the first signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the second address register to output the address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction accompanied by a branch address is detected in the trace information, the execution history tracing section stores the branch address and traces the branch address, and when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction not accompanied by a branch address is detected in the trace information, the execution history tracing section traces the stored branch address.

9. A development support system, comprising: a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when executing the indirect branch instruction, the CPU asserts a first signal and outputs a branch address relating to the indirect branch instruction; a first address register for outputting a stored address when the first signal is asserted to store the branch address output from the CPU, a comparator for comparing the branch address output from the first address register and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first signal; and a second address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the first signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the second address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a second signal when a trace is started, wherein when the second signal is asserted, the memory content of the first address register is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the second address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the second signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address; and an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory, wherein the execution history tracing section operates such that when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction accompanied by a branch address is detected in the trace information, the execution history tracing section stores the branch address and traces the branch address, when an indirect branch instruction is detected in the source program and a code which indicates execution of an indirect branch instruction not accompanied by a branch address is detected in the trace information, the execution history tracing section traces the stored branch address, and when a code which indicates start of a trace is detected in the trace information, the execution history tracing section acquires any one of an execution address and a branch address corresponding to the code from the trace information to trace the acquired address.

10. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, the method comprising the steps of: detecting a call instruction in the source program; detecting a code which indicates execution of an interrupt branch in the trace information; detecting a return instruction in the source program; when any one of the call instruction and the code is detected, acquiring a return address from the source program to push the acquired return address; when any one of the call instruction and the code is detected, acquiring a branch address from the trace information to trace the branch address; and when the return instruction is detected, popping the pushed return address to trace the return address.

11. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which operates such that when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction, when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction; a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted; a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section, wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein when the fourth signal is asserted, the memory content of the stack memory is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first and second signals are negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address, the method comprising the steps of: detecting a call instruction in the source program; detecting a return instruction in the source program; detecting a first code which indicates execution of an interrupt branch in the trace information; detecting a second code which indicates start of a trace in the trace information; when any one of the call instruction and the first code is detected, acquiring a return address from the source program to push the acquired return address; when any one of the call instruction and the first code is detected, acquiring a branch address from the trace information to trace the branch address; when the return instruction is detected, popping the pushed return address to trace the return address; when the second code is detected, initializing the pushed return address; and when the second code is detected, acquiring from the trace information any one of an execution address and a branch address which correspond to the second code to trace the acquired address.

12. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when updating the register, the CPU asserts a first signal, and when executing the indirect branch instruction, the CPU asserts a second signal and outputs a branch address relating to the indirect branch instruction; a loop detection circuit for asserting a third signal during an interval from the assertion of the first signal to the assertion of the second signal; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the second signal; and an address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the second and third signals are asserted, the trace packet control section orders the address register to output the address, the method comprising the steps of: detecting an indirect branch instruction in the source program; detecting a first code which indicates execution of an indirect branch instruction accompanied by a branch address in the trace information; detecting a second code which indicates execution of an indirect branch instruction not accompanied by a branch address in the trace information; when the indirect branch instruction and the first code are detected, storing the branch address which accompanies the first code; when the indirect branch instruction and the first code are detected, tracing the branch address which accompanies the first code; and when the indirect branch instruction and the second code are detected, tracing the stored branch address.

13. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when updating the register, the CPU asserts a first signal, and when executing the indirect branch instruction, the CPU asserts a second signal and outputs a branch address relating to the indirect branch instruction; a loop detection circuit for asserting a third signal during an interval from the assertion of the first signal to the assertion of the second signal; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the second signal; and an address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the second and third signals are asserted, the trace packet control section orders the address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a fourth signal when a trace is started, wherein the loop detection circuit asserts the third signal during an interval from the assertion of the fourth signal to the assertion of the second signal, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the fourth signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the second signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address, the method comprising the steps of: detecting an indirect branch instruction in the source program; detecting a first code which indicates execution of an indirect branch instruction accompanied by a branch address in the trace information; detecting a second code which indicates execution of an indirect branch instruction not accompanied by a branch address in the trace information; detecting a third code which indicates start of a trace in the trace information; when the indirect branch instruction and the first code are detected, storing the branch address which accompanies the first code; when the indirect branch instruction and the first code are detected, tracing the branch address which accompanies the first code; when the indirect branch instruction and the second code are detected, tracing the stored branch address; and when the third code is detected, acquiring any one of an execution address and a branch address which correspond to the third code from the trace information to trace the acquired address.

14. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when executing the indirect branch instruction, the CPU asserts a first signal and outputs a branch address relating to the indirect branch instruction; a first address register for outputting a stored address when the first signal is asserted to store the branch address output from the CPU, a comparator for comparing the branch address output from the first address register and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first signal; and a second address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the first signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the second address register to output the address, the method comprising the steps of: detecting an indirect branch instruction in the source program; detecting a first code which indicates execution of an indirect branch instruction accompanied by a branch address in the trace information; detecting a second code which indicates execution of an indirect branch instruction not accompanied by a branch address in the trace information; when the indirect branch instruction and the first code are detected, storing the branch address which accompanies the first code; when the indirect branch instruction and the first code are detected, tracing the branch address which accompanies the first code; and when the indirect branch instruction and the second code are detected, tracing the stored branch address.

15. A method for tracing an execution history of a source program executed by a CPU of a semiconductor integrated circuit by acquiring from the semiconductor integrated circuit a trace status code and an address as trace information and sequentially collating the source program and the trace information, the semiconductor integrated circuit comprising: a CPU which incorporates an indirect branch instruction of branching to a branch address stored in a register, the CPU operating such that when executing the indirect branch instruction, the CPU asserts a first signal and outputs a branch address relating to the indirect branch instruction; a first address register for outputting a stored address when the first signal is asserted to store the branch address output from the CPU, a comparator for comparing the branch address output from the first address register and the branch address output from the CPU; a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first signal; and a second address register for receiving the branch address output from the CPU and outputting the address under control of the trace packet control section, wherein when the first signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the second address register to output the address, wherein the semiconductor integrated circuit further comprises a synchronization request generation circuit for asserting a second signal when a trace is started, wherein when the second signal is asserted, the memory content of the first address register is initialized, and wherein: when executing an instruction, the CPU outputs an execution address of the executed instruction; the semiconductor integrated circuit includes a selector for selectively outputting any one of the branch address and the execution address output from the CPU; the second address register receives the address output from the selector instead of the branch address output from the CPU and outputs the address under control of the trace packet control section; and the trace packet control section operates such that, when the second signal is asserted, the trace packet control section outputs a code which indicates start of a trace as a trace status code, and in such a case, if the first signal is negated, the trace packet control section orders the selector to select the execution address, and if otherwise, the trace packet control section orders the selector to select the branch address, the method comprising the steps of: detecting an indirect branch instruction in the source program; detecting a first code which indicates execution of an indirect branch instruction accompanied by a branch address in the trace information; detecting a second code which indicates execution of an indirect branch instruction not accompanied by a branch address in the trace information; detecting a third code which indicates start of a trace in the trace information; when the indirect branch instruction and the first code are detected, storing the branch address which accompanies the first code; when the indirect branch instruction and the first code are detected, tracing the branch address which accompanies the first code; when the indirect branch instruction and the second code are detected, tracing the stored branch address; and when the third code is detected, acquiring any one of an execution address and a branch address which correspond to the third code from the trace information to trace the acquired address.