System and Method for Fetching a Boot Code

1. A boot code fetch method of a multi-chip system including a volatile memory chip, a nonvolatile memory chip that stores the boot code, and a host, comprising: transferring the boot code from the nonvolatile memory chip to the volatile memory chip before any processor, including the host, loads or executes the boot code using a DRAM boot controller included in the nonvolatile memory chip; before transferring the boot code from the nonvolatile memory chip to the volatile memory chip, setting a mode register in the volatile memory chip to control the volatile memory chip, wherein setting the mode register of the volatile chip is performed by the nonvolatile chip; and receiving the boot code by the host from the volatile memory chip, wherein the volatile memory chip, the nonvolatile memory chip, and the host are connected to a common system bus.

2. The method of claim 1 , wherein the volatile memory chip is a DRAM chip, and wherein setting the mode register in the DRAM chip includes setting a latency operation mode and a burst length operation mode of the DRAM chip before transferring the boot code from the nonvolatile memory chip to the DRAM chip, and wherein setting the latency operation mode and the burst length operation mode is performed by the non-volatile memory chip.

3. The method of claim 2 , wherein transferring the boot code comprises a step of setting a mode register in the DRAM chip to control the DRAM chip.

4. The method of claim 3 , wherein the setting the mode register of the DRAM chip is performed by the nonvolatile memory chip.

5. The method of claim 4 , wherein the nonvolatile memory chip is a NAND flash memory chip.

6. The method of claim 1 , wherein the volatile memory chip is a DRAM chip; and the nonvolatile memory chip is a NAND flash memory chip including a buffer memory and a DRAM interface unit.

7. The method of claim 6 , wherein transferring the boot code comprises: storing the boot code in the buffer memory; setting a mode register in the DRAM chip; and transferring the boot code stored in the buffer memory to the DRAM chip via the DRAM interface unit after the setting of the mode register.

8. The method of claim 7 , wherein storing the boot code is performed at a power-up in response to a power on reset signal.

9. The method of claim 1 , wherein all of the boot code received by the host is from the volatile memory chip.

10. The method of claim 1 , wherein transferring the boot code to the volatile memory chip is performed by the nonvolatile memory chip.

11. A multi-chip system, comprising: a volatile memory chip; a nonvolatile memory chip configured to store a boot code; and a host configured to fetch the boot code, wherein the nonvolatile memory chip is configured to set a mode register in the volatile memory chip including a latency operation mode and a burst length operation mode of the volatile memory chip prior to a transfer of the boot code to the volatile memory chip, and before any processor, including the host, fetches the boot code.

12. The system of claim 11 , wherein the volatile memory chip is a DRAM chip.

13. The system of claim 11 , wherein the nonvolatile memory chip is a NAND flash memory chip.

14. The system of claim 13 , wherein the NAND flash memory chip comprises: a NAND flash memory configured to store the boot code; a buffer memory configured to store the boot code read from the NAND flash memory; and an interface unit configured to make the NAND flash memory chip interact with the volatile memory chip.

15. The system of claim 14 , wherein a number of the buffer memory is more than one and the buffer memory performs a dual buffering.

16. The system of claim 14 , wherein the buffer memory is an SRAM.

17. The system of claim 11 , wherein the volatile memory chip is a DRAM chip, and the nonvolatile memory chip is a NAND flash memory chip.

18. The system of claim 17 , wherein the NAND flash memory chip comprises: a NAND flash memory in which the boot code is stored; a first buffer memory included in the NAND flash memory chip and configured to store a first portion of the boot code read from the NAND flash memory; a second buffer memory included in the NAND flash memory chip and configured to store a second portion of the boot code read from the NAND flash memory; a mode register configured to store a mode register set information on the DRAM chip; a DRAM interface unit configured to make the NAND flash memory chip interact with the DRAM chip; and a DRAM boot controller configured to: control the boot code stored in the first buffer memory and the second buffer memory to be transferred to the DRAM chip via the DRAM interface unit in response to the mode register set information; transfer the first portion of the boot code from the NAND flash memory chip to the first buffer memory included in the NAND flash memory chip prior to transferring the first portion of the boot code to the DRAM chip; and transfer the second portion of the boot code from the NAND flash memory chip to the second buffer memory included in the NAND flash memory chip prior to transferring the second portion of the boot code to the DRAM chip, and prior to any processor, including the host, accessing the first and second portions of the boot code.

19. The system of claim 18 , wherein a number of the buffer memory is more than one and the buffer memory performs a dual buffering.

20. The system of claim 18 , further comprising: a bootloader configured to control the NAND flash memory and the buffer memory to make the boot code that is stored in the NAND flash memory written into the buffer memory in response to a power-on reset signal at a power-up.

21. A boot code fetch method of a multi-chip system including a volatile DRAM memory chip, a flash memory chip including a NAND flash memory to store the boot code, and a host, the method comprising: before accessing the boot code by any processor, including the host, transferring the boot code from the NAND flash memory to a DRAM interface unit via a first buffer memory and a second buffer memory using a DRAM boot controller located in the flash memory chip, wherein the DRAM interface unit, the first buffer memory, and the second buffer memory are included in the flash memory chip; before transferring the boot code to any processor, including the host, transferring the boot code from the DRAM interface unit to the volatile DRAM memory chip; before transferring the boot code from the DRAM interface unit to the volatile DRAM memory chip, setting a mode register in the volatile DRAM memory chip to control the DRAM memory chip, wherein setting the mode register of the volatile DRAM memory chip is performed by the flash memory chip; and after transferring the boot code to the volatile memory chip, transferring the boot code to the host.

22. The method of claim 21 , wherein the first buffer memory is included in the flash memory chip and separate from the volatile DRAM memory chip, the method further comprising: transferring a first portion of the boot code from the NAND flash memory to the first buffer memory included in the flash memory chip prior to transferring the first portion of the boot code to the separate volatile DRAM memory chip; transferring a second portion of the boot code from the NAND flash memory to the second buffer memory included in the flash memory chip prior to transferring the second portion of the boot code to the separate volatile DRAM memory chip, and prior to any processor, including the host, accessing the first and second portions of the boot code, wherein the second buffer memory is substantially equal in size to the first buffer memory; reading the first portion of the boot code from the first buffer memory; writing the first portion of the boot code to the separate volatile DRAM memory chip; reading the second portion of the boot code from the second buffer memory; and writing the second portion of the boot code to the separate volatile DRAM memory chip, wherein the second portion of the boot code is transferred to the second buffer memory at substantially the same time as the reading and writing of the first portion of the boot code.

23. The method of claim 22 , further comprising: transferring a third portion of the boot code from the NAND flash memory to the first buffer memory, wherein the third portion of the boot code is transferred to the first buffer memory at substantially the same time as the reading and writing of the second portion of the boot code.