System and Method for Managing Copy-On-Write Faults and Change-Protection

1. A method comprising: identifying a shared main memory page containing a physical address corresponding to a virtual address included in an issued write instruction including: determining the selected virtual address is not within a reach of a table lookaside buffer entry that is currently loaded in the table lookaside buffer; if one of a plurality of base and bounds register entries includes the selected virtual address, then identifying one of the plurality of the base and bounds register entries that includes the selected virtual address; calculating a new table lookaside buffer entry that includes the selected virtual address; and loading the new table lookaside buffer entry in the table lookaside buffer.

2. The method of claim 1 , wherein the write instruction is a first write instruction, and wherein the method of identifying a shared main memory page containing a physical address corresponding to a virtual address included in the first write instruction is included in a copy-on-write (COW) fault including: forking a parent process to create a child process; assigning parent's virtual-to-physical address translations read-only status wherein the first write instruction is issued from a first issuing process, the first issuing process being a first one of the parent process or the child process; and issuing a copy-on-write fault to the first issuing process.

3. The method of claim 2 , further including: creating a copy of the shared main memory page; assigning the copy of the shared main memory page to the first issuing process including assigning a read write status to the copy of the shared main memory page for the first issuing process; and reissuing the first write instruction from the first issuing process.

4. The method of claim 2 , further including: issuing a second write instruction from a second one of the parent process or the child process; and issuing a copy-on-write fault to the second issuing process.

5. The method of claim 4 , further including: assigning parent's virtual-to-physical address translations read-write status to the second issuing process; and reissuing the second write instruction.

6. The method of claim 2 , wherein the status of the shared main memory page is maintained in the table lookaside buffer and a corresponding entry in the base and bounds registers.

7. The method of claim 1 , wherein the write instruction is a third write instruction and wherein the method of identifying a shared main memory page containing a physical address corresponding to a virtual address is included in a change-protection process including: sharing a plurality of main memory pages between a plurality of processes, wherein the third write instruction is issued from a third issuing process, the third issuing process being one of the plurality of processes; requesting the identified shared main memory page be assigned a write status for the third issuing process; assigning write access to the third issuing process for the identified shared main memory page; reissuing the third write instruction; writing data to the identified shared main memory page; requesting the identified shared main memory page be assigned a read-only status for each of the plurality of processes; and assigning read-only access to the plurality of processes for the identified shared main memory page.

8. The method of claim 7 , wherein the status of the shared main memory page is maintained in the table lookaside buffer and a corresponding entry in the base and bounds registers.

9. A computer system comprising: a main memory; a processor die coupled to the main memory by a first bus, the processor die including a processor core coupled to a first cache memory and a plurality of base and bounds registers, each one of the plurality of base and bounds registers having a base virtual address field, an ending virtual address field and a base physical address field, the first cache memory having a table lookaside buffer entry stored therein; logic for identifying a shared main memory page containing a physical address corresponding to a virtual address included in an issued write instruction including: logic for determining the selected virtual address is not within a reach of a table lookaside buffer entry that is currently loaded in the table lookaside buffer; if one of a plurality of base and bounds register entries includes the selected virtual address, then identifying one of the plurality of the base and bounds register entries that includes the selected virtual address; logic for calculating a new table lookaside buffer entry that includes the selected virtual address; and logic for loading the new table lookaside buffer entry in the table lookaside buffer.

10. The system of claim 9 , wherein the write instruction is a first write instruction, and wherein the logic for identifying a shared main memory page containing a physical address corresponding to a virtual address included in the first write instruction is included in a copy-on-write (COW) fault includes: logic for forking a parent process to create a child process; logic for assigning parent's virtual-to-physical address translations read-only status wherein the first write instruction is issued from a first issuing process, the first issuing process being a first one of the parent process or the child process; and logic for issuing a copy-on-write fault to the first issuing process.

11. The system of claim 9 , wherein the write instruction is a third write instruction and wherein the logic for identifying a shared main memory page containing a physical address corresponding to a virtual address is included in a change-protection process includes: logic for sharing a plurality of main memory pages between a plurality of processes, wherein the third write instruction is issued from a third issuing process, the third issuing process being one of the plurality of processes; logic for requesting the identified shared main memory page be assigned a write status for the third issuing process; logic for assigning write access to the third issuing process for the identified shared main memory page; logic for reissuing the third write instruction; logic for writing data to the identified shared main memory page; logic for requesting the identified shared main memory page be assigned a read-only status for each of the plurality of processes; and logic for assigning read-only access to the plurality of processes for the identified shared main memory page.

12. The system of claim 9 , wherein the write instruction is a first write instruction, and wherein the logic for identifying a shared main memory page containing a physical address corresponding to a virtual address included in the first write instruction is included in a copy-on-write (COW) fault including: logic for forking a parent process to create a child process; logic for assigning parent's virtual-to-physical address translations read-only status wherein the first write instruction is issued from a first issuing process, the first issuing process being a first one of the parent process or the child process; and logic for issuing a copy-on-write fault to the first issuing process wherein the status of the shared main memory page is maintained in the table lookaside buffer and a corresponding entry in the base and bounds registers.

13. The system of claim 10 , further including: logic for creating a copy of the shared main memory page; logic for assigning the copy of the shared main memory page to the first issuing process including assigning a read write status to the copy of the shared main memory page for the first issuing process; and logic for reissuing the first write instruction from the first issuing process.

14. The system of claim 10 , further including: logic for issuing a second write instruction from a second one of the parent process or the child process; and logic for issuing a copy-on-write fault to the second issuing process.

15. The system of claim 14 , further including: logic for assigning parent's virtual-to-physical address translations read-write status to the second issuing process; and logic for reissuing the second write instruction.