Method and System for Image Scaling Output Timing Calculation and Remapping

1. An image scaling system for scaling video signal data between different formatted display devices, said image scaling system comprising: a video processing unit; an image scaling unit; a timing generator; and a remapping logic unit configured for: calculating a number of extra pixels based on a parameter by: calculating an expected number of input pixels based on a first format and calculating an expected number of output pixels based on a second format; calculating an input frame rate by multiplying an input clock cycle time by the expected number of input pixels; setting an output frame rate to the calculated input frame rate, wherein the output frame rate is a product of an output clock cycle time and a sum of the expected number of output pixels and the number of extra pixels; and calculating the number of extra pixels by dividing the input frame rate by the output clock cycle and subtracting the expected number of output pixels; and remapping at least one extra pixel to an offset position in at least one previous scan line, thereby eliminating the rendering of a short or a long scan line during image conversion between a first display device having the first format and a second display device having the second format.

2. The image scaling system of claim 1 , wherein the image scaling unit comprises an input vertical synchronization (Vsync) signal unit for receiving vertical synchronization signals from an input video signal being scaled.

3. The image scaling system of claim 2 , wherein the image scaling unit further comprises an output timing reset logic unit for generating reset signals for signal counters during a rising edge of the input vsync signal.

4. The image scaling system of claim 1 , wherein the remapping logic unit is configured to determine the at least one previous scan line based on the calculated number of extra pixels to enable a scaled image to appropriately fit a designated display panel.

5. The image scaling system of claim 4 , wherein the image scaling unit further comprises a vertical signal line counter for counting the number of vertical lines in each video signal scaled.

6. The image scaling system of claim 5 , wherein the image scaling unit further comprises a horizontal signal pixel counter for counting the number horizontal pixels in each video signal scaled.

7. The image scaling system of claim 6 , wherein the vertical signal line counter includes comparator logic for determining when a total vertical line count is equal to a vertical line count.

8. The image scaling system of claim 7 , wherein the image scaling unit further comprises a display phase lock loop unit for generating output clock signals in a specified programmed frequency for each scaled line in the scaled image.

9. An image scaling circuit for scaling video data to a corresponding display panel format, the image scaling circuit comprising: a signal input buffer unit for receiving an input stream of pixel data of a first size; a signal output buffer unit for outputting a stream of pixel data of a second size; and a video data scaling unit for: calculating a number of extra pixels based on a parameters by: calculating an expected number of input pixels based on the first size and calculating an expected number of output pixels based on the second size; calculating an input frame rate by multiplying an input clock cycle time by the expected number of input pixels; setting an output frame rate to the calculated input frame rate, wherein the output frame rate is a product of an output clock cycle time and a sum of the expected number of output pixels and the number of extra pixels; and calculating the number of extra pixels by dividing the input frame rate by the output clock cycle and subtracting the expected number of output pixels; and remapping at least one extra pixel to an offset position in at least one previous scan line, thereby eliminating the rendering of a short or a long scan line during image conversion between the pixel data of the first size to the pixel data of the second size to fit a designated format display panel.

10. The image scaling circuit of claim 9 , wherein the pixel data of the second size is a scaled version of the pixel data of the first size.

11. The image scaling circuit of claim 10 , wherein the video data scaling unit further remaps the pixel data of the first size to the pixel data of the second size to avoid long lines and short lines while generating the output video stream of pixel data.

12. The image scaling circuit of claim 11 , wherein the video data scaling unit further synchronizes input timing signals of a received video signal to the output timing signals of corresponding scaled output video signals to prevent distorted images to the designated display panel.

13. The image scaling circuit of claim 9 , wherein the video data scaling unit comprises an input vertical synchronization (Vsync) signal unit for receiving vertical synchronization signals from an input video signal being scaled.

14. The image scaling circuit of claim 13 , wherein the video data scaling unit further comprises an output timing reset_logic unit for generating reset signals for signal counters during a rising edge of the input vsync signal.

15. The image scaling circuit of claim 9 , wherein the video data scaling unit further comprises remapping logic for determining the at least one previous scan line based on the calculated number of extra pixels to enable a scaled image to appropriately fit a designated display panel.

16. The image scaling circuit of claim 15 , wherein the video data scaling unit further comprises a vertical signal line counter for counting the number of vertical lines in each video signal scaled.

17. The image scaling circuit of claim 16 , wherein the video data scaling unit further comprises a horizontal signal pixel counter for counting the number of horizontal pixels in each video signal scaled.

18. The image scaling circuit of claim 16 , wherein the vertical signal line counter include comparator logic for determining when a total vertical line count is equal to a vertical line count.

19. The image scaling circuit of claim 18 , wherein the video data image scaling unit further comprises a display phase lock loop unit for generating output clock signals in a specified programmed frequency for each scaled line in the scaled image.

20. An image scaling circuit for scaling video data to a corresponding display panel format, the image scaling circuit comprising: a signal input buffer unit for receiving an input stream of pixel data of a first size; a signal output buffer unit for outputting a stream of pixel data of a second size; and remapping logic for: calculating a number of extra pixels based on a parameters by: calculating an expected number of input pixels based on the first size and calculating an expected number of output pixels based on the second size; calculating an input frame rate by multiplying an input clock cycle time by the expected number of input pixels; setting an output frame rate to the calculated input frame rate, wherein the output frame rate is a product of an output clock cycle time and a sum of the expected number of output pixels and the number of extra pixels; and calculating the number of extra pixels by dividing the input frame rate by the output clock cycle and subtracting the expected number of output pixels; and remapping at least one extra pixel to an offset position in at least one previous scan line, thereby eliminating the rendering of a short or a long scan line during image conversion between the pixel data of the first size to the pixel data of the second size to fit a designated format display panel.

21. A method of scaling video signals from a first format display panel to a second display panel of a second format, the method comprising: during an initialization process of the second display panel, calculating a number of extra pixels based on a parameters by: calculating an expected number of input pixels based on a first format and calculating an expected number of output pixels based on a second format; calculating an input frame rate by multiplying an input clock cycle time by the expected number of input pixels; setting an output frame rate to the calculated input frame rate, wherein the output frame rate is a product of an output clock cycle time and a sum of the expected number of output pixels and the number of extra pixels; and calculating the number of extra pixels by dividing the input frame rate by the output clock cycle and subtracting the expected number of output pixels; selecting a horizontal pixel offset value; selecting a scan line in the frame of the second format having a base horizontal line length, wherein the selected scan line is a previous scan line to the last scan line; determining whether to extend the base horizontal line length of the selected scan line by the horizontal pixel offset value based on the calculated number of extra pixels; if the selected scan line is extended, remapping at least one extra pixel to at least one offset position in the extended scan line; selecting a next scan line in the frame of the second format having the base horizontal line length; and repeating the determining, the remapping, and the next scan line selecting processes until the selected scan line is the last scan line, such that each extra pixel is remapped to an extended scan line.