Semiconductor Nonvolatile Memory Trimming Technique for Output Characteristic Control and Redundancy Repair

1. A semiconductor nonvolatile memory comprising: a memory array in which a plurality of first nonvolatile memory cells are arranged; a plurality of memory areas which are arranged in the memory array and have a plurality of second nonvolatile memory cells in which the same predetermined information is stored; a sequence circuit which generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on; a write-read unit which writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal; a latch circuit which latches the predetermined information which is read by the write-read unit, based on the latch selection signal; and a selection-drive unit which selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells, wherein the plurality of second nonvolatile memory cells respectively store logical information values of both 0 and 1 as the predetermined information, and the sequence circuit comprises a determination unit, wherein the determination unit carries out repeated cycles of reading the plurality of second nonvolatile memory cells through the write-read unit in a read operation when the power is turned on, determines whether or not all of the read logical values are matched with the logical information values, and causes the write-read unit to read the predetermined information when all of the read logical values are matched with the logical information values.

2. The semiconductor nonvolatile memory of claim 1 , wherein a trimming logical value is changed until a determination result by the determination unit is matched.

3. The semiconductor nonvolatile memory of claim 1 , wherein the plurality of memory areas are sequentially read until a determination result by the determination unit is matched.

4. A semiconductor nonvolatile memory comprising: a memory array in which a plurality of first nonvolatile memory cells are arranged; a plurality of memory areas which are arranged in the memory array and have a plurality of second nonvolatile memory cells in which the same predetermined information is stored; a sequence circuit which generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on; a write-read unit which writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal; a latch circuit which latches the predetermined information which is read by the write-read unit, based on the latch selection signal; and a selection-drive unit which selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells, wherein the sequence circuit comprises a determination unit, and wherein the determination unit reads the predetermined information which is stored in each of the plurality of second nonvolatile memory cells and carries out a computation on the read predetermined information in a read operation when the power is turned on, after reading all of the predetermined information, compares the computed predetermined information and information which is read through the write-read unit and which was computed and written in advance when the predetermined information was written to the second nonvolatile memory cells, and reads the predetermined information of the second nonvolatile memory cells through the write-read unit until a comparison result of the computed predetermined information and the information computer and written in advance match.