Syncword Detecting Circuit and a Baseband Signal Receiving Circuit

1. A syncword detecting circuit for detecting a predetermined syncword in an input baseband signal, comprising: a matched-bit-number comparing circuit that determines a number of bits in the baseband signal that match bits of a predetermined syncword, and that compares said number with a first threshold; a comparing-result-change detecting circuit that samples a result of said matched-bit-number comparing circuit by a clock having a frequency equivalent to an integer N greater than or equal to two times a symbol transmission rate of the baseband signal, and that detects a change of said result of said matched-bit-number comparing circuit; a detected-result storing circuit that stores sequentially a result of said comparing-result-change detecting circuit and to also store historical data of results of said comparing-result-change detecting circuit of previous cycle periods; a total-number detecting circuit that detects a total number of said results of said matched-bit-number comparing circuit from a present cycle period and the previous cycle periods, said results of said matched-bit-number comparing circuit being included in cycle periods of said clock surpassing said first threshold, based on the results of said comparing-result-change detecting circuit stored in said detected-result storing circuit; and a syncword detecting circuit that detects said predetermined syncword based on a total-number result of said total-number detecting circuit, and that selects an intermediate phase of a cycle period having a maximum number of bits that match as a detection phase.

2. The syncword detecting circuit according to claim 1 , where said total-number detecting circuit that provides a present detecting result from said comparing-result-change detecting circuit, and a last detecting result stored in said detected-result storing circuit.

3. The syncword detecting circuit according to claim 2 , wherein said predetermined syncword is detected at an instance said total-number result surpasses a second threshold and has become less than a previous cycle period, and said intermediate phase of said cycle period and an intermediate phase of that previous cycle period are detected based on a number of that previous cycle period from when detecting results surpass said first threshold until detecting of said predetermined syncword is completed and a clock phase when said predetermined syncword is detected.

4. The syncword detecting circuit according to claim 3 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

5. The syncword detecting circuit according to claim 2 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit number with said first threshold.

6. The syncword detecting circuit according to claim 1 , wherein said predetermined syncword is detected at an instance said total-number result surpasses a second threshold and has become less than a previous cycle period, and said intermediate phase of said cycle period and an intermediate phase of that previous cycle period are detected based on a number of that previous cycle period from when detecting results surpass said first threshold until detecting of said predetermined syncword is completed and a clock phase when said predetermined syncword is detected.

7. The syncword detecting circuit according to claim 6 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

8. The syncword detecting circuit according to claim 1 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

9. A baseband signal receiving circuit comprising: a sampling circuit that samples a baseband signal at a clock phase given from N types of phase in a clock having a frequency equivalent to N times a symbol transmission rate, N being an integer greater than or equal to two; and a syncword detecting circuit that detects a syncword included in said baseband signal, said syncword detecting circuit including a matched-bit-number comparing circuit that determines a number of bits in the baseband signal that match bits of a predetermined syncword, and that compares said number with a first threshold, a comparing-result-change detecting circuit that samples a result of said matched-bit-number comparing circuit by a clock having a frequency equivalent to an integer greater than or equal to two times a symbol transmission rate of the baseband signal, and that detects a change of said result of said matched-bit-number comparing circuit, a detected-result storing circuit that stores sequentially a result of said comparing-result-change detecting circuit, and that also stores historical data of results of said comparing-result-change detecting circuit of previous cycle periods, a total-number detecting circuit that detects a total number of said results of said matched-bit-number comparing circuit from a present cycle period and the previous cycle periods, said results of said matched-bit-number comparing circuit being included in cycle periods of said clock surpassing said first threshold, based on the results of said comparing-result-change detecting circuit stored in said detected-result storing circuit, and a syncword detecting circuit that detects said predetermined syncword based on a total-number result of said total-number detecting circuit, and that selects an intermediate phase of a cycle period having a maximum number of bits that match as a detection phase.

10. The baseband signal receiving circuit according to claim 9 , wherein said total-number detecting circuit provides a present detecting result from said comparing-result-change detecting circuit, and a last detecting result stored in said detected-result storing circuit.

11. The baseband signal receiving circuit according to claim 10 , wherein said predetermined syncword is detected at an instance said total-number result surpasses a second threshold and has become less than a previous cycle period, and said intermediate phase of said cycle period and an intermediate phase of that previous cycle period are detected based on a number of that previous cycle period from when detecting results surpass said first threshold until detecting of said predetermined syncword is completed and a clock phase when said predetermined syncword is detected.

12. The baseband signal receiving circuit according to claim 11 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

13. The baseband signal receiving circuit according to claim 10 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

14. The baseband signal receiving circuit according to claim 9 , wherein said predetermined syncword is detected at an instance said total-number result surpasses a second threshold and has become less than a previous cycle period, and said intermediate phase of said cycle period and an intermediate phase of that previous cycle period are detected based on a number of that previous cycle period from when detecting results surpass said first threshold until detecting of said predetermined syncword is completed and a clock phase when said predetermined syncword is detected.

15. The baseband signal receiving circuit according to claim 14 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.

16. The baseband signal receiving circuit according to claim 9 , wherein said matched-bit-number comparing circuit includes, a high-speed-sampling data storing unit that sequentially stores data sampled by said clock, a data extracting unit that extracts data stored in said high-speed-sampling data storing unit by a number equal to a number of bits of said predetermined syncword with said extracted data having a time difference corresponding to N cycles of said clock to each other, and a matched-bit number comparing unit that acquires a matched-bit-number in said extracted data that matches the bits in said predetermined syncword, and compares said matched-bit-number with said first threshold.