Reusing a Buffer Memory as a Microcache for Program Instructions of a Detected Program Loop

1. Apparatus for processing data, said apparatus comprising: a cache memory; a buffer memory, coupled to said cache memory, and configured to operate in both a buffer mode and a microcache mode, wherein said buffer mode is a mode buffering instruction data associated with accesses to said cache memory, and said microcache mode is a mode storing instruction data, and accesses to said instruction data are made from said buffer memory without an associated access to said cache memory; a loop detector responsive to memory addresses of instructions for detecting program loops; and buffer control circuitry, coupled to said loop detector and said buffer memory and responsive to detection of a program loop by said loop detector, for switching said buffer memory from operating in said buffer mode to operating in said microcache mode with instruction data for at least a portion of said program loop being stored within said buffer memory.

2. Apparatus as claimed in claim 1 , wherein said loop detector detects a non-sequential fetch of an instruction from a memory address at a backward location relative to normal program flow as indicating a program loop.

3. Apparatus as claimed in claim 2 , wherein said loop detector does not detect as a program loop a non-sequential fetch from a preceding memory address requiring a change in memory address value greater than a predetermined range.

4. Apparatus as claimed in claim 1 , comprising prefetch circuitry coupled to an external memory and arranged to prefetch instruction data to be executed, said prefetch circuitry including branch prediction circuitry serving as at least part of said loop detection circuitry.

5. Apparatus as claimed in claim 1 , wherein, upon entering said microcache mode, said buffer control circuitry controls said instruction data to be read from said cache memory and stored in said buffer memory.

6. Apparatus as claimed in claim 1 , wherein, when said program loop comprises more instruction data than can be stored in said buffer memory, a portion of said instruction data comprising said program loop are stored in said buffer memory and a remainder of said instruction data comprising said program loop are stored in said cache memory.

7. Apparatus as claimed in claim 1 , wherein said buffer memory stores one or more values indicative of memory addresses of said instruction data stored in said buffer memory when operating in said microcache mode.

8. Apparatus as claimed in claim 1 , wherein when operating in said buffer mode said buffer memory functions as one or more of: (i) a linefill buffer to store instruction data fetched from an external memory to be stored into said cache memory upon a cache miss; and (ii) a prefetch buffer to store instruction data speculatively fetched from said external memory based upon predictions of instruction data to be accessed; and (iii) a decoupling buffer to store instruction data read from said cache memory for execution.

9. Apparatus as claimed in claim 8 , wherein when operating as a prefetch buffer some instruction data speculatively fetched to said buffer memory is not written to said cache memory.

10. Apparatus for processing data, said apparatus comprising: a cache memory means for storing instruction data; a buffer memory means coupled to said cache memory means, said buffer memory means configured to operate in a buffer mode and in a microcache mode wherein in said buffer mode said buffer memory means comprises a means for buffering instruction data associated with accesses to said cache memory means, and in said microcache mode said buffer memory means comprises a means for storing instruction data, where accesses to said instruction data are made from said buffer memory means without an associated access to said cache memory means; loop detector means for detecting program loops in response to memory addresses of instructions; and buffer control means, coupled to said loop detector means and said buffer memory means, for switching, in response to detection of a program loop by said loop detector, said buffer memory means from operating in said buffer mode to operating in said microcache mode with instruction data for at least a portion of said program loop being stored within said buffer memory means.

11. A method of processing data, said method comprising the steps of: storing instruction data within a cache memory; storing instruction data within a buffer memory, said buffer memory coupled to said cache memory and arranged to operate in a buffer mode and in a microcache mode, wherein said buffer mode is a mode including the step of buffering instruction data associated with accesses to said cache memory and said microcache mode is a mode including the step of storing instruction data, where accesses to said instruction data are made from said buffer memory without an associated access to said cache memory; in response to memory addresses of instructions, detecting program loops; and in response to detection of a program loop, switching said buffer memory from operating in said buffer mode to operating in said microcache mode with instruction data for at least a portion of said program loop being stored within said buffer memory.

12. A method as claimed in claim 11 , wherein a non-sequential fetch of an instruction from a memory address at a backward location relative to normal program flow is detected as indicating a program loop.

13. A method as claimed in claim 12 , wherein a non-sequential fetch from a preceding memory address requiring a change in memory address value greater than a predetermined range is not detected as a program loop.

14. A method as claimed in claim 11 , comprising prefetching instruction data to be executed and performing branch prediction as at least part of said step of detecting.

15. A method as claimed in claim 11 , further comprising, upon entering said microcache mode, controlling said instruction data to be read from said cache memory and stored in said buffer memory.

16. A method as claimed in claim 11 , wherein, when said program loop comprises more instruction data than can be stored in said buffer memory, storing a portion of said instruction data comprising said program loop in said buffer memory and storing a remainder of said instruction data comprising said program loop in said cache memory.

17. A method as claimed in claim 11 , wherein said buffer memory stores one or more values indicative of memory addresses of said instruction data stored in said buffer memory when operating in said microcache mode.

18. A method as claimed in claim 11 , wherein when operating in said buffer mode said buffer memory functions as one or more of: (i) a linefill buffer to store instruction data fetched from an external memory to be stored into said cache memory upon a cache miss; and (ii) a prefetch buffer to store instruction data speculatively fetched from said external memory based upon predictions of instruction data to be accessed; and (iii) a decoupling buffer to store instruction data read from said cache memory for execution.

19. A method as claimed in claim 18 , wherein when operating as a prefetch buffer some instruction data speculatively fetched to said buffer memory is not written to said cache memory.

20. Apparatus for processing data, said apparatus comprising: a cache memory; a buffer memory, coupled to said cache memory and configured to operate in either: (i) a buffer mode buffering instruction data associated with accesses to said cache memory; or (ii) a microcache mode storing instruction data, accesses to said instruction data are made from said buffer memory without an associated access to said cache memory; a loop detector responsive to memory addresses of instructions to detect program loops; and buffer control circuitry, coupled to said loop detector and said buffer memory and responsive to detection of a program loop by said loop detector, to switch said buffer memory from operating in said buffer mode to operating in said microcache mode with instruction data for at least a portion of said program loop being stored within said buffer memory, wherein, upon entering said microcache mode, said buffer control circuitry controls said instruction data to be read from said cache memory and stored in said buffer memory.

21. A method of processing data, said method comprising the steps of: storing instruction data within a cache memory; storing instruction data within a buffer memory coupled to said cache memory and arranged to operate in either: (i) a buffer mode buffering instruction data associated with accesses to said cache memory; or (ii) a microcache mode storing instruction data, accesses to said instruction data being made from said buffer memory without an associated access to said cache memory; in response to memory addresses of instructions, detecting program loops; and in response to detection of a program loop, switching said buffer memory from operating in said buffer mode to operating in said microcache mode with instruction data for at least a portion of said program loop being stored within said buffer memory, further comprising, upon entering said microcache mode, controlling said instruction data to be read from said cache memory and stored in said buffer memory.