Static Timing Analysis and Dynamic Simulation for Custom and ASIC Designs

1. A method for verifying timing of a circuit using a single tool, the circuit having a first portion with a gate-level description and a second portion with a transistor-level description, comprising: accepting both the gate-level and transistor-level descriptions; and using the single tool to perform timing analysis of the circuit using both the gate-level and transistor-level descriptions, wherein the step of using the single tool includes decomposing circuit structures into transistor-level descriptions to determine timing information associated with the transistor-level descriptions.

2. The method according to claim 1 , wherein the step of using a single tool includes obtaining timing information associated with the gate-level descriptions from a pre-characterized timing library.

3. The method according to claim 1 , wherein the decomposing step includes: identifying unique circuit structures associated with certain of the transistor-level descriptions; and performing function check to obtain the associated timing information.

4. The method according to claim 1 , further comprising: using the single tool to perform timing simulation of the circuit using both the gate-level and transistor-level descriptions.

5. The method according to claim 1 , wherein the accepting step includes reading the gate-level and transistor-level descriptions from a SPICE netlist.

6. A method for verifying timing of a circuit using a single tool, comprising: accepting descriptions of the circuit; obtaining timing information associated with the descriptions; and using the single tool to perform both timing analysis and timing simulation of the circuit using the descriptions and timing information, wherein the single tool includes a delay calculator that is capable of performing timing analysis of individual logic structures within the circuit, as well as performing timing simulation of the circuit as a whole.

7. The method according to claim 6 , wherein the step of using a single tool includes partitioning the circuit based on the descriptions.

8. The method according to claim 6 , wherein the descriptions include both gate-level and transistor-level descriptions.