Test Access Port

1. An apparatus comprising: at least one test control mechanism; a multi-core processor including a plurality of cores, wherein at least one core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers; and said multi-core processor and said test control mechanism having a configuration so as to allow testing of said multi-core processor, said test control mechanism tests more than one core of the plurality of cores concurrently.

2. The apparatus of claim 1 , wherein said multi-core processor comprises at least two processor cores and at least one circuit comprising non-processor core logic.

3. The apparatus of claim 2 , wherein said at least one circuit comprising non-core logic includes said plurality of distributed data registers and said plurality of control registers.

4. The apparatus of claim 3 , wherein said at least one test control mechanism is substantially compliant with the IEEE 1149.1 specification.

5. The apparatus of claim 3 , wherein said TAPC, said plurality of distributed data registers, and said plurality of distributed control registers are coupled via an Integrated Test Bus (ITB).

6. The apparatus of claim 3 , wherein said test control mechanism is controllable, at least in part, by one of said TAPC.

7. The apparatus of claim 6 , wherein which one of said test TAPC controls said test control mechanism is dynamically selectable during operation.

8. The apparatus of claim 2 , wherein at least one of the said at least two processor cores comprises a test access port (TAP) which includes said TAPC.

9. The apparatus of claim 8 , wherein said test control mechanism and said at least two processor cores are coupled so as to provide multiple coupling arrangements, said multiple coupling arrangements being dynamically selectable during operation.

10. The apparatus of claim 9 , wherein said multiple coupling arrangements are selected from a group consisting essentially of coupling said test access port substantially in series, coupling said test access ports substantially in parallel and coupling said test access ports for substantially independent operation.

11. The apparatus of claim 8 , wherein said test control mechanism is arranged to allow at least one of said at least two processor cores' said TAP to be externally knowable from said multi-core processor.

12. The apparatus of claim 11 , wherein said test control mechanism is arranged to allow only one of said at least two processor cores' said TAP to be externally visible from said multi-core processor.

13. The apparatus of claim 11 , wherein said test control mechanism is arranged to allow the selection of which at least one of said at least two processor cores' said TAP is externally visible from said multi-core processor to occur dynamically.

14. The apparatus of claim 8 , wherein said test control mechanism is coupled to produce during operation an error signal if the output signals of said at least two processor cores' said TAP are not substantially equivalent.

15. The apparatus of claim 2 , wherein said test control mechanism, at least one processor core and said at least one circuit comprising non-processor core logic are further coupled so as to allow testing of said at least one circuit comprising non-processor core logic.

16. A system comprising: a computing platform, including: a memory to store instructions; a multi-core processor to process instructions, said multi-core processor including: a test control mechanism, a plurality of processor cores, at least one circuit comprising non-processor core logic, and wherein at least one processor core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers; and said multi-core processor and said test control mechanism having a configuration so as to allow testing of said plurality of processor cores, said test control mechanism tests more than one processor core of the plurality of processor cores concurrently.

17. A method comprising: providing an indicator to identify a desired testing option; based upon said desired testing option, dynamically routing signals between a plurality of test access ports (TAPs) during testing, wherein said plurality of TAPs are part of a multi-core processor; and said multi-processor core including a plurality of processor cores, wherein at least one processor core includes a test access port controller (TAPC), a plurality of distributed data registers and a plurality of distributed control registers.

18. The method of claim 17 , wherein the routing of said signals is selected from a group consisting essentially of coupling said test access ports substantially in series, coupling said test access ports substantially in parallel, and coupling said test access ports for substantially independent operation.

19. The method of claim 18 , wherein providing an indicator to identify a desired testing option comprises storing control information in a register.

20. The method of claim 19 , wherein storing control information in a register comprises a step in compliance with the operation of test data registers as described in the IEEE 1149.1 specification.

21. The method of claim 17 , wherein dynamically routing signals between said plurality of TAPs comprises dynamically routing signals between said TAPC and said plurality of distributed data registers and said plurality of control registers.

22. The method of claim 17 , wherein dynamically routing signals between said plurality of TAPs comprises only altering the routing of signals external to said plurality of processor cores.

23. The method of claim 17 , which further comprises producing a signal that indicates whether the output signals of said at least two processor cores' said plurality of TAPs are equivalent or substantially equivalent.