Semiconductor Integrated Circuit

1. A semiconductor integrated circuit having a clock distribution circuit including a plurality of subordinate clock trees, comprising: a first subordinate clock tree; a second subordinate clock tree; a phase-locked loop for comparing a reference clock and an output clock of a first end clock driver contained in the first subordinate clock tree; a first phase comparator for comparing an output clock of the first end clock driver with an output clock of a second end clock driver contained in the second subordinate clock tree; and a first variable delay circuit provided for corresponding to the second subordinate clock tree, wherein a clock with a phase adjusted by the phase-locked loop is inputted to the clock distribution circuit, a clock delayed by the first variable delay circuit is inputted to the second sub block tree, an amount of delay of the first variable delay circuit is controlled by the first phase comparator so that a phase of an output clock of the first end clock driver becomes equal to a phase of an output clock of the second end clock driver, and a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree equals to a relative position of the first end clock driver in the end clock driver of the first subordinate clock tree.

2. The semiconductor integrated circuit according to claim 1 , further comprising: a third subordinate clock tree; a second phase comparator for comparing an output clock of the second end clock driver with an output clock of the third end clock driver contained in the third subordinate clock tree; and a second variable delay circuit provided for corresponding to the third subordinate clock tree, wherein a clock delayed by the second variable delay circuit is inputted to the third subordinate clock tree, and an amount of delay of the second variable delay circuit is controlled by the second phase comparator so that a phase of an output clock of the second end clock driver becomes equal to a phase of an output clock of the third end clock driver, and a relative position of the third end clock driver in the end clock driver of the third subordinate clock tree equals to a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree.

3. The semiconductor integrated circuit according to claim 1 , wherein the clock distribution circuit is an H-tree clock distribution circuit.

4. The semiconductor integrated circuit according to claim 3 , wherein the clock distribution circuit comprises a plurality of clock driver levels, and the first and the second subordinate clock trees include the same number of clock driver levels.

5. A semiconductor integrated circuit having a clock distribution circuit including a plurality of subordinate clock trees, comprising: a first subordinate clock tree; a second subordinate clock tree; a phase-locked loop for comparing a reference clock and an output clock of a first end clock driver contained in the first subordinate clock tree; and a first delay circuit provided for corresponding to the second subordinate clock tree; wherein a clock with a phase adjusted by the phase-locked loop is inputted to the clock distribution circuit, a clock delayed by a first predetermined amount of delay by the first delay circuit is inputted to the second sub block tree, the first predetermined amount of delay is obtained so that a phase of an output clock of the first end clock driver becomes equal to a phase of an output clock of the second end clock driver contained in the second subordinate clock tree, and a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree equals to a relative position of the first end clock driver in the end clock driver of the first subordinate clock tree.

6. The semiconductor integrated circuit according to claim 5 , wherein the first predetermined amount of delay is stored in a nonvolatile memory.

7. The semiconductor integrated circuit according to claim 5 , further comprising: a third subordinate clock tree; and a second delay circuit provided for corresponding to the third subordinate clock tree, wherein a clock delayed by a second predetermined amount of delay by the second delay circuit is inputted to the third sub block tree, the second predetermined amount of delay is obtained so that a phase of an output clock of the second end clock driver becomes equal to a phase of an output clock of the third end clock driver contained in the third subordinate clock tree, and a relative position of the third end clock driver in the end clock driver of the third subordinate clock tree equals to a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree.

8. The semiconductor integrated circuit according to claim 7 , wherein the second predetermined amount of delay is stored in a nonvolatile memory.

9. The semiconductor integrated circuit according to claim 5 , wherein the clock distribution circuit is an H-tree clock distribution circuit.

10. The semiconductor integrated circuit according to claim 9 , wherein the clock distribution circuit comprises a plurality of clock driver levels, and the first and the second subordinate clock trees include the same number of clock driver levels.

11. The semiconductor integrated circuit according to claim 5 , further comprising: a phase comparator for comparing an output clock of the first end clock driver with an output clock of a second end clock driver, wherein the operation of the first phase comparator can be stopped by a control signal.

12. The semiconductor integrated circuit according to claim 7 , further comprising: a phase comparator for comparing an output clock of the second end clock driver with an output clock of the third end clock driver, wherein the operation of the second phase comparator can be stopped by a control signal.

13. A semiconductor integrated circuit having a clock distribution circuit including a plurality of subordinate clock trees, comprising: a first subordinate clock tree; a second subordinate clock tree; and a delay circuit provided for corresponding to the second subordinate clock tree, wherein a clock delayed by a predetermined amount of delay by the delay circuit is inputted to the second sub block tree, the predetermined amount of delay is obtained so that a phase of an output clock of the first end clock driver contained in the first subordinate clock tree becomes equal to a phase of an output clock of the second end clock driver contained in the second subordinate clock tree, and a relative position of the second end clock driver in the end clock driver of the second subordinate clock tree equals to a relative position of the first end clock driver in the end clock driver of the first subordinate clock tree.

14. The semiconductor integrated circuit according to claim 13 , wherein the predetermined amount of delay is stored in a nonvolatile memory.

15. The semiconductor integrated circuit according to claim 13 , wherein the clock distribution circuit is an H-tree clock distribution circuit.

16. The semiconductor integrated circuit according to claim 15 , wherein the clock distribution circuit comprises a plurality of clock driver levels, and the first and the second subordinate clock trees include the same number of clock driver levels.

17. The semiconductor integrated circuit according to claim 13 , further comprising: a phase comparator for comparing an output clock of the first end clock driver with an output clock of the second end clock driver, wherein the operation of the phase comparator can be stopped by a control signal.