Method, System, and Apparatus for Memory Compression with Flexible In-Memory Cache

1. An apparatus comprising: a main memory including: a compression cache to store a plurality of uncompressed data, wherein the compression cache is organized as a sectored cache that has associated tags that are on-die, wherein a tag match is performed between a memory access request and the associated tags and a hit signal is sent to a memory controller coupled to the main memory to schedule an uncompressed data access from the compression cache if a hit occurs; a compressed memory to store a plurality of compressed data; and a compressed memory pointer table (CMPT) to store a plurality of pointers, the apparatus to assign a higher priority to read operations of the compressed memory in comparison to other operations to the compressed memory.

2. The apparatus of claim 1 wherein the compression cache has a plurality of associated tags that are incorporated within a memory interface coupled to the apparatus.

3. The apparatus of claim 2 , wherein the memory interface comprises: a victim buffer to store at least one entry that has been evicted from the compression cache; a CMPT offset calculator to provide an offset relative to the start of the CMPT based on an actual address of data to be compressed and stored in the compression cache.

4. The apparatus of claim 3 wherein the memory interface is incorporated within a chipset coupled between a processor and the main memory.

5. The apparatus of claim 4 wherein the apparatus is incorporated within a memory controller hub (MCH) of the chipset.

6. The apparatus of claim 3 wherein the entry is to be evicted based on a first in first out (FIFO) protocol.

7. The apparatus of claim 1 wherein the plurality of pointers are to access the plurality of compressed data based on a plurality of cache block addresses.

8. The apparatus of claim 1 wherein the CMPT is to store the plurality of pointers to the plurality of compressed data sequentially based on memory addresses for the plurality of compressed data.

9. An apparatus for a memory interface comprising: the memory interface including: a first cache to store a plurality of tags for a compression cache of a main memory coupled to the memory interface, the compression cache to store a plurality of uncompressed data; a victim buffer to store at least one entry that has been evicted from the compression cache and to directly supply the at least one entry to a requester if a tag match occurs in the victim buffer; an offset calculator to provide an offset relative to the start for a Compressed Memory Pointer Table (CMPT) of the main memory that is to store pointers to compressed data stored in a compressed memory of the main memory, based on an actual address of a data being compressed; and a second cache to store a plurality of pointers for the CMPT, the apparatus to assign a higher priority to read operations of the compressed memory in comparison to other operations to the compressed memory.

10. The apparatus of claim 9 wherein the memory interface is incorporated within a chipset coupled between a processor and the main memory.

11. The apparatus of claim 10 wherein the apparatus is incorporated within a memory controller hub (MCH) of the chipset.

12. The apparatus of claim 9 wherein the entry is evicted based on a first in first out (FIFO) protocol.

13. A method comprising: receiving a memory address for a memory operation; storing a plurality of compressed data in a compressed memory in a main memory; performing a tag match between the memory address and a first cache of a memory interface coupled to the main memory storing a plurality of tags for a compression cache in the main memory; and accessing a plurality of uncompressed data from the compression cache responsive to an uncompressed access scheduling by a memory controller if the tag match resulted in a hit, and if the tag match resulted in a miss, accessing the plurality of uncompressed data directly from a victim buffer of the memory interface that stores uncompressed data evicted from the compressed memory if the plurality of uncompressed data is present in the victim buffer.

14. The method of claim 13 further comprising locating a pointer in a pointer cache of the memory interface if present therein, otherwise using an offset address obtained from an offset calculator of the memory interface to locate the pointer in a pointer table of the main memory and subsequently finding a compressed memory location based at least in part on the pointer if the tag match resulted in a miss for the memory operation for a read miss.

15. The method of claim 13 further comprising compressing the data and storing it in a compressed memory location for the memory operation for a write miss.

16. A system comprising: a processor; and a main memory, coupled to the processor, with: a compression cache to store a plurality of uncompressed data, wherein the compression cache is organized as a sectored cache that has associated tags that are on-die, wherein a tag match is performed between a memory access request and the associated tags and a hit signal is sent to a memory controller coupled to the main memory to schedule an uncompressed data access from the compression cache if a hit occurs; a compressed memory to store a plurality of compressed data; and a compressed memory pointer table (CMPT) to store a plurality of pointers, and to assign a higher priority to read operations of the compressed memory in comparison to other operations to the compressed memory.

17. The system of claim 16 wherein the compression cache has a plurality of associated tags that are incorporated within a memory interface.

18. The system of claim 16 wherein the plurality of pointers are to the plurality of compressed data based on a plurality of cache block addresses.

19. A system comprising: a processor; and a memory interface, coupled to the processor, with: a first cache to store a plurality of tags for a compression cache of a main memory coupled to the memory interface, the compression cache to store a plurality of uncompressed data; a memory controller to schedule an uncompressed data access from the compression cache if a tag match operation between the plurality of tags and an access request results in a hit; a victim buffer to store at least one entry that has been evicted from the compression cache; an offset calculator to provide an offset relative to the start of a Compressed Memory Pointer Table (CMPT) of the main memory that is to store pointers to compressed data stored in a compressed memory of the main memory, based on an actual address of a data being compressed; and a second cache to store a plurality of most recently used pointers for the CMPT.

20. The system of claim 19 wherein the memory interface is incorporated within a chipset coupled between the processor and the main memory.

21. The system of claim 19 wherein the entry is evicted based on a first in first out (FIFO) protocol.

22. A system comprising: a processor, coupled to a memory bridge, the memory bridge to comprise; a first cache to store a plurality of tags for a compression cache of a main memory coupled to the memory bridge, the first cache to perform a tag match operation between the plurality of tags and an incoming memory address; a victim buffer to store at least one entry that has been evicted from the compression cache; a memory controller to schedule an uncompressed data access from the compression cache if the tag match operation results in a hit; an offset calculator to provide an offset relative to the start of a Compressed Memory Pointer Table (CMPT) of the main memory that is to store pointers to compressed data stored in a compressed memory of the main memory, based on an actual address of a data that is compressed; and a second cache to store a plurality of pointers for the CMPT address; and the main memory, coupled to the memory bridge, to comprise; the compression cache to store a plurality of uncompressed data; a compressed memory to store a plurality of compressed data; and a compressed memory pointer table (CMPT) to store a plurality of pointers.

23. The system of claim 22 wherein the compression cache is a sectored cache.

24. The system of claim 22 wherein the compression cache has a plurality of associated tags that are incorporated within the memory bridge.

25. The system of claim 22 wherein the plurality of pointers are to the plurality of compressed data based on a plurality of cache block addresses.