System and Method for Gigabit Media Independence Interface (gmii)-To-System Packet Interface Level 3 (spi-3) Interface Translation

1. A system for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, comprising: a translation circuit translating a GMII reception signal received from a GMII interface device into an SPI-3 reception signal synchronized with an SPI3 reference clock, and translating an SPI-3 transmission signal received from an SPI-3 interface device into a GMII transmission signal synchronized with a GMII reference clock, said translation circuit comprising: first translation means for translating the GMII reception signal received from the GMII interface device into the SPI-3 reception signal synchronized with the SPI3 reference clock based on starting frame delimiter (SFD) pattern information in the GMII reception signal; and second translation means for translating the SPI-3 transmission signal received from the SPI-3 interface device into the GMII transmission signal synchronized with the GMII reference clock by adding the SFD pattern information to the SPI-3 transmission signal; said first translation means comprising: an SFD pattern detector for detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; a first clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and a first controller for translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock from the first clock synchronizer when the SFD pattern information received from the SFD pattern detector matches pre-stored SFD pattern information.

2. The system according to claim 1 , said GMII reception signal being received from the GMII interface device in synchronization with a GMII_RXC clock signal only when a GMII RX_DV (Data Valid) signal is high.

3. The system according to claim 1 , said first controller comprising: a comparator for comparing the SFD pattern information received from the SFD pattern detector to the pre-stored SFD pattern information, and for generating a match signal when they match; a GMII receiving controller for synchronizing the GMII reception signal with the GMII reference clock in response to the match signal generated by the comparator; and an SPI-3 receiving controller for translating the GMII reception signal synchronized by the GMII receiving controller into the SPI-3 reception signal according to the SPI3 reference clock.

4. The system according to claim 1 , said second translation means comprising: a second clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the SPI-3 transmission signal into the GMII transmission signal; an SFD pattern information generator for generating preamble and SFD pattern information according to a reference clock signal from the second clock synchronizer; and a second controller for translating the generated preamble and SFD pattern information from the SFD pattern information generator, and the SPI-3 transmission signal, into the GMII transmission signal according to the GMII reference clock from the second clock synchronizer.

5. The system according to claim 4 , said second controller comprising: an SPI-3 transmission controller for synchronizing the SPI-3 transmission signal with the SPI3 reference clock; and a GMII transmission controller for translating the SPI-3 transmission signal synchronized by the SPI-3 transmission controller into the GMII transmission signal according to the GMII reference clock.

6. A system for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, comprising: a first translation circuit for translating a GMII reception signal received from the GMII interface device into an SPI-3 reception signal synchronized with an SPI3 reference clock based on starting frame delimiter (SFD) pattern information in the GMII reception signal; and a second translation circuit for translating an SPI-3 transmission signal received from an SPI-3 interface device into a GMII transmission signal synchronized with a GMII reference clock by adding the SFD pattern information to the SPI-3 transmission signal; said first translation circuit comprising: an SFD pattern detector for detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; a first clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and a first controller for translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock from the first clock synchronizer when the SFD pattern information received from the SFD pattern detector matches pre-stored SFD pattern information.

7. The system according to claim 6 , said GMII reception signal being received from the GMII interface device in synchronization with the GMII_RXC clock signal only when a GMII RX_DV (Data Valid) signal is high.

8. The system according to claim 6 , said first controller comprising: a comparator for comparing the SFD pattern information received from the SFD pattern detector to the pre-stored SFD pattern information, and for generating a match signal when they match; a GMII receiving controller for synchronizing the GMII reception signal with the GMII reference clock in response to the match signal generated by the comparator; and an SPI-3 receiving controller for translating the GMII reception signal synchronized by the GMII receiving controller into the SPI-3 reception signal according to the SPI3 reference clock.

9. The system according to claim 6 , said second translation circuit comprising: a second clock synchronizer for performing clock synchronization with the GMII reference clock and the SPI3 reference clock upon translating the SPI-3 transmission signal into the GMII transmission signal; an SFD pattern information generator for generating preamble and SFD pattern information according to a reference clock signal from the second clock synchronizer; and a second controller for translating the generated preamble and SFD pattern information from the SFD pattern information generator, and the SPI-3 transmission signal, into the GMII transmission signal according to the GMII reference clock from the second clock synchronizer.

10. The system according to claim 9 , said second controller comprising: an SPI-3 transmission controller for synchronizing the SPI-3 transmission signal with the SPI3 reference clock; and a GMII transmission controller for translating the SPI-3 transmission signal synchronized by the SPI-3 transmission controller into the GMII transmission signal according to the GMII reference clock.

11. A method for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, the method comprising the steps of: receiving a GMII reception signal from a GMII interface device; and translating the GMII reception signal received from the GMII interface device into an SPI-3 reception signal synchronized with an SPI3 reference clock based on starting frame delimiter (SFD) pattern information in the GMII reception signal, wherein the step of translating the GMII reception signal received from the GMII interface device into the SPI-3 reception signal synchronized with the SPI3 reference clock comprises: detecting the SFD pattern information from the GMII reception signal received from the GMII interface device; performing clock synchronization with a GMII reference clock and the SPI3 reference clock upon translating the GMII reception signal into the SPI-3 reception signal; and translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock when the detected SFD pattern information matches pre-stored SFD pattern information.

12. The method according to claim 11 , wherein the GMII reception signal is received from the GMII interface device in synchronization with a GMII_RXC clock signal only when a GMII RX_DV (Data Valid) signal is high.

13. The method according to claim 11 , wherein the step of translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock comprises: comparing the detected SFD pattern information to the pre-stored SFD pattern information, and generating a match signal when they match; synchronizing the GMII reception signal with the GMII reference clock in response to receiving the match signal; and translating the GMII reception signal into the SPI-3 reception signal according to the SPI3 reference clock.

14. A method for gigabit media independence interface (GMII)-to-system packet interface level 3 (SPI-3) interface translation, the method comprising the steps of: receiving an SPI 3 transmission signal from an SPI-3 interface device; and translating the SPI-3 transmission signal received from the SPI-3 interface device into a GMII transmission signal synchronized with a GMII reference clock by adding starting frame delimiter (SFD) pattern information to the SPI-3 transmission signal, wherein the step of translating the SPI-3 transmission signal received from the SPI-3 interface device into the GMII transmission signal synchronized with the GMII reference clock by adding the SFD pattern information to the SPI-3 transmission signal comprises: performing clock synchronization with the GMII reference clock and an SPI3 reference clock; generating preamble and SFD pattern information according to the GMII reference clock; and translating the preamble and SFD pattern information, and the SPI-3 transmission signal, into the GMII transmission signal according to the GMII reference clock.

15. The method according to claim 14 , wherein the step of translating the preamble and SFD pattern information, and the SPI-3 transmission signal, into the GMII transmission signal according to the GMII reference clock comprises: synchronizing the SPI-3 transmission signal with an SPI3 reference clock; and translating the SPI-3 transmission signal synchronized with the SPI3 reference clock into the GMII transmission signal according to the GMII reference clock.