Driver Circuit , Electro-Optical Device, and Electronic Instrument

1. A driver circuit for driving data lines of an electro-optical device, the driver circuit comprising: an operational amplifier which drives the data line by a rail-to-rail operation or a non-rail-to-rail operation based on a grayscale voltage corresponding to one of first to Pth (P is an integer of four or more) grayscale values; and an operational amplifier control section which causes the operational amplifier to perform the rail-to-rail operation or the non-rail-to-rail operation based on grayscale data; when the sth (1≦s≦P, s is an integer) grayscale value corresponding to the grayscale data is in a range of the qth (1<q<P, q is an integer) to rth (q<r<P, r is an integer) grayscale values, the operational amplifier driving the data line by the non-rail-to-rail operation based on the grayscale voltage corresponding to the sth grayscale value; and when the sth grayscale value is not in the range of the qth to rth grayscale values, the operational amplifier driving the data line by the rail-to-rail operation based on the grayscale voltage corresponding to the sth grayscale value.

2. The driver circuit as defined in claim 1 , wherein the operational amplifier control section causes the operational amplifier to perform the rail-to-rail operation or the non-rail-to-rail operation for the grayscale value in the range of the qth to rth grayscale values based on higher-order two-bit data of the grayscale data; and wherein, when the operation of the operational amplifier has been switched by the operational amplifier control section so that the operational amplifier performs the rail-to-rail operation for the grayscale value in the range of the qth to rth grayscale values, the operational amplifier drives the data line by the rail-to-rail operation regardless of the grayscale value.

3. The driver circuit as defined in claim 1 , comprising: a comparison section which compares the grayscale voltage corresponding to the qth grayscale value with a first threshold value, and compares the grayscale voltage corresponding to the rth grayscale value with a second threshold value; wherein the operational amplifier control section causes the operational amplifier to perform the rail-to-rail operation or the non-rail-to-rail operation for the grayscale value in the range of the qth to rth grayscale values based on a comparison result of the comparison section; and wherein, when the operation of the operational amplifier has been switched by the operational amplifier control section so that the operational amplifier performs the rail-to-rail operation for the grayscale value in the range of the qth to rth grayscale values, the operational amplifier drives the data line by the rail-to-rail operation regardless of the grayscale value.

4. The driver circuit as defined in claim 3 , wherein the operational amplifier control section causes the operational amplifier to perform the non-rail-to-rail operation for the grayscale value in the range of the qth to rth grayscale values on condition that the grayscale voltage corresponding to the qth grayscale value is equal to or less than the first threshold value and the grayscale voltage corresponding to the rth grayscale value is equal to or greater than the second threshold value, or the grayscale voltage corresponding to the rth grayscale value is equal to or greater than the first threshold value and the grayscale voltage corresponding to the qth grayscale value is equal to or less than the second threshold value.

5. The driver circuit as defined in claim 3 , comprising: a threshold storage section which stores the first and second threshold values corresponding to a power supply voltage range of the operational amplifier and an output amplitude voltage supplied to the data line; wherein the comparison section performs the comparison based on information stored in the threshold storage section.

6. The driver circuit as defined in claim 5 , comprising: an output amplitude voltage setting register for setting the output amplitude voltage; and an offset voltage setting register for setting an offset voltage for the output amplitude voltage; wherein the comparison section performs the comparison based on the information stored in the threshold storage section corresponding to the output amplitude voltage set in the output amplitude voltage setting register and an addition result of the output amplitude voltage and the offset voltage set in the offset voltage setting register.

7. The driver circuit as defined in claim 1 , wherein the operational amplifier includes: a first conductivity type differential amplifier circuit which includes a first conductivity type first differential transistor pair, sources of the transistors being connected with a first current source and an input signal and an output signal being respectively input to gates of the transistors, and a first current mirror circuit which generates drain currents of the transistors of the first differential transistor pair; a second conductivity type differential amplifier circuit which includes a second conductivity type second differential transistor pair, sources of the transistors being connected with a second current source and the input signal and the output signal being respectively input to gates of the transistors, and a second current mirror circuit which generates drain currents of the transistors of the second differential transistor pair; a first auxiliary circuit which drives at least one of a first output node and a first inversion output node which are drains of the transistors of the first differential transistor pair based on the input signal and the output signal; a second auxiliary circuit which drives at least one of a second output node and a second inversion output node which are drains of the transistors of the second differential transistor pair based on the input signal and the output signal; and an output circuit which includes a second conductivity type first driver transistor of which gate voltage is controlled based on voltage of the first output node, and a first conductivity type second driver transistor of which a drain is connected with a drain of the first driver transistor and of which gate voltage is controlled based on voltage of a second output node, and outputs voltage of the drain of the first driver transistor as the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the first differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the first auxiliary circuit controls the gate voltage of the first driver transistor by driving at least one of the first output node and the first inversion output node; wherein, when an absolute value of a gate-source voltage of the transistor of the second differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the second auxiliary circuit controls the gate voltage of the second driver transistor by driving at least one of the second output node and the second inversion output node; and wherein the operational amplifier control section stops or limits an operating current of at least one of the first and second auxiliary circuits, whereby the operational amplifier performs the non-rail-to-rail operation.

8. The driver circuit as defined in claim 1 , wherein the operational amplifier includes: a first conductivity type differential amplifier circuit which amplifies a difference between an input signal and an output signal; a second conductivity type differential amplifier circuit which amplifies the difference between the input signal and the output signal; a first auxiliary circuit which drives at least one of a first output node and a first inversion output node of the first conductivity type differential amplifier circuit based on the input signal and the output signal; a second auxiliary circuit which drives at least one of a second output node and a second inversion output node of the second conductivity type differential amplifier circuit based on the input signal and the output signal; and an output circuit which generates the output signal based on voltages of the first and second output nodes; wherein the first conductivity type differential amplifier circuit includes: a first current source to which a first power supply voltage is supplied at one end; a first conductivity type first differential transistor pair, sources of the transistors being connected with the other end of the first current source, drains of the transistors being respectively connected with the first output node and the first inversion output node, and the input signal and the output signal being respectively input to gates of the transistors; and a first current mirror circuit which includes a second conductivity type first transistor pair of which gates are connected, a second power supply voltage being supplied to sources of the transistors of the first transistor pair, drains of the transistors being respectively connected with the first output node and the first inversion output node, and the drain and the gate of the transistor of the first transistor pair which is connected with the first inversion output node being connected; wherein the second conductivity type differential amplifier circuit includes: a second current source to which the second power supply voltage is supplied at one end; a second conductivity type second differential transistor pair, sources of the transistors being connected with the other end of the second current source, drains of the transistors being respectively connected with the second output node and the second inversion output node, and the input signal and the output signal being respectively input to gates of the transistors; and a second current mirror circuit which includes a first conductivity type second transistor pair of which gates are connected, the first power supply voltage being supplied to sources of the transistors of the second transistor pair, drains of the transistors being respectively connected with the second output node and the second inversion output node, and the drain and the gate of the transistor of the second transistor pair which is connected with the second inversion output node being connected; wherein the output circuit includes a first conductivity type second driver transistor of which a gate is connected with the second output node, and a second conductivity type first driver transistor of which a gate is connected with the first output node and a drain is connected with a drain of the second driver transistor, and outputs voltage of the drain of the first driver transistor as the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the first differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the first auxiliary circuit controls a gate voltage of the first driver transistor by driving at least one of the first output node and the first inversion output node; wherein, when an absolute value of a gate-source voltage of the transistor of the second differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the second auxiliary circuit controls a gate voltage of the second driver transistor by driving at least one of the second output node and the second inversion output node; and wherein the operational amplifier control section stops or limits an operating current of at least one of the first and second auxiliary circuits, whereby the operational amplifier performs the non-rail-to-rail operation.

9. The driver circuit as defined in claim 7 , wherein the first auxiliary circuit includes: first conductivity type first and second current driver transistors, the first power supply voltage being supplied to sources of the first and second current driver transistors and drains of the first and second current driver transistors being respectively connected with the first output node and the first inversion output node; and a first current control circuit which controls gate voltages of the first and second current driver transistors based on the input signal and the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the first differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the first current control circuit controls the gate voltages of the first and second current driver transistors so that at least one of the first output node and the first inversion output node is driven; and wherein the operational amplifier control section stops or limits an operating current of the first current control circuit.

10. The driver circuit as defined in claim 8 , wherein the first auxiliary circuit includes: first conductivity type first and second current driver transistors, the first power supply voltage being supplied to sources of the first and second current driver transistors and drains of the first and second current driver transistors being respectively connected with the first output node and the first inversion output node; and a first current control circuit which controls gate voltages of the first and second current driver transistors based on the input signal and the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the first differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the first current control circuit controls the gate voltages of the first and second current driver transistors so that at least one of the first output node and the first inversion output node is driven; and wherein the operational amplifier control section stops or limits an operating current of the first current control circuit.

11. The driver circuit as defined in claim 7 , wherein the second auxiliary circuit includes: second conductivity type third and fourth current driver transistors, the second power supply voltage being supplied to sources of the third and fourth current driver transistors and drains of the third and fourth current driver transistors being respectively connected with the second output node and the second inversion output node; and a second current control circuit which controls gate voltages of the third and fourth current driver transistors based on the input signal and the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the second differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the second current control circuit controls the gate voltages of the third and fourth current driver transistors so that at least one of the second output node and the second inversion output node is driven; and wherein the operational amplifier control section stops or limits an operating current of the second current control circuit.

12. The driver circuit as defined in claim 8 , wherein the second auxiliary circuit includes: second conductivity type third and fourth current driver transistors, the second power supply voltage being supplied to sources of the third and fourth current driver transistors and drains of the third and fourth current driver transistors being respectively connected with the second output node and the second inversion output node; and a second current control circuit which controls gate voltages of the third and fourth current driver transistors based on the input signal and the output signal; wherein, when an absolute value of a gate-source voltage of the transistor of the second differential transistor pair to which the input signal is input at the gate is smaller than an absolute value of a threshold voltage of the transistor, the second current control circuit controls the gate voltages of the third and fourth current driver transistors so that at least one of the second output node and the second inversion output node is driven; and wherein the operational amplifier control section stops or limits an operating current of the second current control circuit.

13. The driver circuit as defined in claim 9 , wherein the first current control circuit includes: a third current source to which the second power supply voltage is supplied at one end; a second conductivity type third differential transistor pair, sources of the transistors being connected with the other end of the third current source and the input signal and the output signal being respectively input to gates of the transistors; and first conductivity type fifth and sixth current driver transistors, the first power supply voltage being supplied to sources of the fifth and sixth current driver transistors, drains of the fifth and sixth current driver transistors being respectively connected with the drains of the transistors of the third differential transistor pair, and a gate and a drain of each of the fifth and sixth current driver transistors being connected; wherein the drain of the transistor of the third differential transistor pair to which the input signal is input at the gate is connected with the gate of the second current driver transistor; wherein the drain of the transistor of the third differential transistor pair to which the output signal is input at the gate is connected with the gate of the first current driver transistor; and wherein the operational amplifier control section stops or limits current of the third current source.

14. The driver circuit as defined in claim 10 , wherein the first current control circuit includes: a third current source to which the second power supply voltage is supplied at one end; a second conductivity type third differential transistor pair, sources of the transistors being connected with the other end of the third current source and the input signal and the output signal being respectively input to gates of the transistors; and first conductivity type fifth and sixth current driver transistors, the first power supply voltage being supplied to sources of the fifth and sixth current driver transistors, drains of the fifth and sixth current driver transistors being respectively connected with the drains of the transistors of the third differential transistor pair, and a gate and a drain of each of the fifth and sixth current driver transistors being connected; wherein the drain of the transistor of the third differential transistor pair to which the input signal is input at the gate is connected with the gate of the second current driver transistor; wherein the drain of the transistor of the third differential transistor pair to which the output signal is input at the gate is connected with the gate of the first current driver transistor; and wherein the operational amplifier control section stops or limits current of the third current source.

15. The driver circuit as defined in claim 9 , wherein the second current control circuit includes: a fourth current source to which the first power supply voltage is supplied at one end; a first conductivity type fourth differential transistor pair, sources of the transistors being connected with the other end of the fourth current source and the input signal and the output signal being respectively input to gates of the transistors; and second conductivity type seventh and eighth current driver transistors, the second power supply voltage being supplied to sources of the seventh and eighth current driver transistors, drains of the seventh and eighth current driver transistors being respectively connected with the drains of the transistors of the fourth differential transistor pair, and a gate and a drain of each of the seventh and eighth current driver transistors being connected; wherein the drain of the transistor of the fourth differential transistor pair to which the input signal is input at the gate is connected with the gate of the fourth current driver transistor; wherein the drain of the transistor of the fourth differential transistor pair to which the output signal is input at the gate is connected with the gate of the third current driver transistor; and wherein the operational amplifier control section stops or limits current of the fourth current source.

16. The driver circuit as defined in claim 10 , wherein the second current control circuit includes: a fourth current source to which the first power supply voltage is supplied at one end; a first conductivity type fourth differential transistor pair, sources of the transistors being connected with the other end of the fourth current source and the input signal and the output signal being respectively input to gates of the transistors; and second conductivity type seventh and eighth current driver transistors, the second power supply voltage being supplied to sources of the seventh and eighth current driver transistors, drains of the seventh and eighth current driver transistors being respectively connected with the drains of the transistors of the fourth differential transistor pair, and a gate and a drain of each of the seventh and eighth current driver transistors being connected; wherein the drain of the transistor of the fourth differential transistor pair to which the input signal is input at the gate is connected with the gate of the fourth current driver transistor; wherein the drain of the transistor of the fourth differential transistor pair to which the output signal is input at the gate is connected with the gate of the third current driver transistor; and wherein the operational amplifier control section stops or limits current of the fourth current source.

17. An electro-optical device comprising: a plurality of scan lines; a plurality of data lines; a plurality of pixels; a scan line driver circuit which scans the scan lines; and the driver circuit as defined in claim 1 which drives the data lines.

18. An electronic instrument comprising the electro-optical device as defined in claim 17 .