Interface Apparatus and Method for Synchronization of Data

1. An interface apparatus for synchronous interchange of a data word between two circuit blocks comprising: a data input configured to receive a data word, and a data output configured to output the data word; a first register device and a second parallel-connected register device, each having an input coupled to the data input, a selection input, and an output, and each configured to store a data word applied on the input side and to emit the data word at the respective output; a selection circuit, connected to the output of the first register device and to the output of the second register device, and configured to selectively couple the output of the first or the second register device to the data output as a function of a control signal provided thereto; a first clock input configured to receive a first clock signal; a second clock input configured to receive a second clock signal; a synchronization circuit, coupled to the first and the second clock input and having a control output coupled to the selection circuit, and configured to emit a selection signal that is derived from the first clock signal for selection of the first or the second register device for storage of a data word applied to the data input, and wherein the synchronization circuit further comprises a sampling apparatus which is clocked with the second clock signal and is configured to emit the control signal at the control output, wherein the control signal is derived from the selection signal and the second clock signal, and wherein the sampling apparatus is configured to detect a change in the selection signal, and wherein the sampling apparatus comprises a first and at least one second flipflop circuit having data inputs configured to receive the selection signal, with a clock input of the first flipflop circuit being connected to the second clock input, and a clock input of the at least one second flipflop circuit being connected via at least one first delay element in order to delay the second clock signal in time, to the second clock input.

2. The interface apparatus of claim 1 , wherein the first and the second register device each comprise a clock signal input which respectively forms the selection input for the first and the second register device, and wherein the first and the second register device are configured to emit a data word which is applied to their respective data input at their output on a flank of a clock signal coupled thereto respectively, which is derived from the selection signal.

3. The interface apparatus of claim 1 , further comprising a first buffer circuit connected between the data input of the interface apparatus and the first and second register devices, and configured to emit a data word which has been applied to the data input of the interface apparatus to the first and second register devices on a clock flank of the first clock signal.

4. The interface apparatus of claim 1 , further comprising a second buffer circuit connected between the selection circuit and the data output of the interface apparatus, and configured to emit a data word which is applied to the selection circuit to the data output on a clock flank of the second clock signal.

5. The interface apparatus of claim 1 , wherein the synchronization circuit comprises a second selection circuit which is configured to produce the selection signal for selection of the respective other register device during each clock period of the first clock signal.

6. The interface apparatus of claim 5 , wherein the second selection circuit comprises a flipflop circuit which is clocked with the first clock signal and whose data output is connected via an inverter to a first input of a first logic gate, to a first input of a second logic gate, and via the inverter to its data input.

7. The interface apparatus of claim 6 , wherein a second input of the first logic gate and a second input of the second logic gate are coupled to the first clock input, and the output of the first logic gate is coupled to the selection input of the first register device, and the output of the second logic gate is coupled to the selection input of the second register device.

8. The interface apparatus of claim 6 , wherein the first and the second logic gate each comprise a logic AND gate.

9. The interface apparatus of claim 1 , wherein the selection circuit is configured to assume two states, with the output of the first register device being coupled to the data output of the interface apparatus in a first state, and with the output of the second register device being coupled to the data output of the interface apparatus in a second state.

10. The interface apparatus of claim 1 , wherein the sampling apparatus further comprises a third flipflop circuit having a clock input coupled via a second delay element to the second clock input, and a data input connected via at least one logic gate to the data outputs of the first and the at least one second flipflop circuit.

11. The interface apparatus of claim 10 , wherein the clock input of the third flipflop circuit is connected via the second delay element and the at least one first delay element to the second clock input.

12. A method for synchronization of a data word between two circuit blocks which are clocked at the same frequency, comprising: providing a first register device and a second register device for alternating storage of a data word which is emitted from the first circuit block; selecting one of the two register devices based on a state of a selection signal which is associated with the respective register device, comprising: producing the selection signal at a first logic level and at a second logic level, which is inverted with respective clock periods of a first clock signal, wherein the first logic level is associated with the first register device, and the second logic level is associated with the second register device; transferring the data word emitted from the first circuit block to the selected register device at a timing associated with a clock flank of the first clock signal; detecting a state change in the selection signal with a second clock signal and a delayed version of the second clock signal; determining a time at which the data word can be emitted from the selected register device to the second circuit block; transferring the data word which has been received in the selected register device to a second circuit block after detection of the occurrence of a clock flank of the second clock signal.

13. The method of claim 12 , wherein selecting one of the two register devices comprises: applying the selection signal and the first clock to a first logic gate; and inverting the selection signal and applying the inverted selection signal and the first clock signal to a second logic gate.

14. The method of claim 12 , wherein selecting one of the two register devices comprises: producing a third and a fourth clock signal at half the clock frequency of the first clock signal, with the third clock signal having a phase shift of half the clock period with respect to the fourth clock signal; and supplying the third and fourth clock signals to a respective clock input of the first and second register devices, wherein the register devices are configured to receive a data word which has been emitted from a first circuit block on each clock flank of the third and fourth clock signals, respectively.

15. The method of claim 12 , wherein transferring the data word comprises: producing a control signal; switching a switching device using the control signal; and transferring the data word to the second circuit block on the occurrence of a clock flank of the second clock signal.

16. An interface apparatus for synchronous interchange of a data word between two circuit blocks comprising: a first register device and a second register device, respectively comprising an input for receiving a data word, a selection input, and an output for emitting the data word, and respectively configured to store the data word; a selection circuit, coupled to the output of the first register device and to the output of the second register device, and configured to selectively couple the output of the first or the second register device to a data output of the interface apparatus as a function of a control signal provided thereto; a first clock input configured to receive a first clock signal; a second clock input configured to receive a second clock signal; a synchronization circuit, coupled to the first and the second clock input and having a control output coupled to the selection circuit, and configured to emit a selection signal that is derived from the first clock signal for selection of the first or the second register device for storage of a data word applied to the input respectively, and wherein the synchronization circuit further comprises a sampling apparatus which is clocked with the second clock signal and is configured to emit the control signal at the control output, wherein the control signal is derived from the selection signal and the second clock signal, and wherein the sampling apparatus is configured to detect a change in the selection signal, and wherein the sampling apparatus comprises a first and at least one second flipflop circuit having data inputs configured to receive the selection signal, with a clock input of the first flipflop circuit being coupled to the second clock input, and a clock input of the at least one second flipflop circuit being coupled via at least one first delay element in order to delay the second clock signal in time, to the second clock input.

17. The interface apparatus of claim 16 , wherein the synchronization circuit comprises a second selection circuit which is configured to produce the selection signal for selection of the respective other register device during respective clock periods of the first clock signal, the selection signal comprising a first logic level and a second logic level, which is inverted with respective clock periods of the first clock signal, wherein the first logic level is associated with the first register device, and the second logic level is associated with the second register device.

18. The interface apparatus of claim 16 , wherein the first and the second register device respectively comprise a clock signal input which respectively forms the selection input for the first and the second register device, and wherein the first and the second register device are configured to emit a data word which is applied to their respective input at their output on a flank of a clock signal coupled thereto respectively, which is derived from the selection signal.

19. The interface apparatus of claim 18 , comprising: a third and a fourth clock input configured to receive a third and a fourth clock signal respectively at half the clock frequency of the first clock signal, with the third clock signal having a phase shift of half the clock period with respect to the fourth clock signal; and wherein the respective clock input of the first and second register devices is configured to receive the third and the fourth clock signal, wherein the register devices are configured to receive a data word which has been emitted from a first circuit block on a respective clock flank of the third and fourth clock signals, respectively.

20. The interface apparatus of claim 16 , comprising a first buffer circuit coupled between a data input of the interface apparatus and the first and second register devices, and configured to emit a data word which has been applied to the data input of the interface apparatus to the first and second register devices on a clock flank of the first clock signal.