Parallel Processing Computer

1. A parallel processing computer for executing a plurality of threads concurrently and in parallel, said computer comprising: a thread activation controller for determining whether or not each of threads, which are exclusively executable program fragments, is ready-to-run, and to put the thread determined ready-to-run into a ready thread queue as ready-to-run thread; and a thread execution controller having a pre-load unit, an EU (Execution Unit) allocation and trigger unit, a plurality of thread execution units and a plurality of register files including a plurality of registers, and wherein the pre-load unit, prior to when each ready-to-run thread in the ready thread queue is executed, allocates a free register file of the plurality of register files to the each ready-to-run thread, to load initial data for the each ready-to-run thread into the allocated register file, and wherein the EU allocation and trigger unit, when there is a thread execution unit in idle state of the plurality of thread execution units, retrieves ready-to-run thread from the top of the ready thread queue, and to allocate the retrieved ready-to-run thread to the thread execution unit in idle state, and to couple the register file loaded the initial data for the ready-to-run thread with the allocated thread execution unit in idle state, and to activate the ready-to-run thread, and wherein the plurality of thread execution units execute the activated threads concurrently in parallel; and wherein the thread activation controller comprises synchronous control memory, and wherein the synchronous control memory has blocks for every instance, each block having both a count field for synchronously activating thread and a preceding-thread number field in which preceding thread number is previously stored therein for each thread.

2. The parallel processing computer according to claim 1 , wherein the plurality of thread execution units are coupled to instruction caches, each of which is dedicated to each thread execution unit, respectively, and wherein the parallel processing computer further comprises a first memory manager, said first memory manager, before ready-to-run thread is triggered, loading the code of the ready-to-run thread into the instruction cache from the memory.

3. The parallel processing computer according to claim 1 , further comprising data caches, and wherein the pre-load unit accesses the data caches before accessing the memory, and if data for executing is found in any of the data caches the pre-load unit loads the found data for executing from the data caches.

4. The parallel processing computer according to claim 3 , wherein the data caches include a plurality of memory banks, and wherein the parallel processing computer further comprises a second memory manager, and wherein the second memory manager, when executing each thread if there is any memory bank of the data caches which was used by the thread which precedes the each thread, is controlled to use the any memory bank.

5. The parallel processing computer according to claim 1 , wherein the thread activation controller sets preceding thread number, which is set in the preceding-thread number field as an initial value, in the count field, to decrement the value in the count field by one when each activation notice is received, and to determine that the thread is ready-to-run if the value reaches zero.

6. The parallel processing computer according to claim 4 , wherein the thread activation controller sets preceding thread number, which is set in the preceding-thread number field as an initial value, in the count field, to decrement the value in the count field by one when each activation notice is received, and to determine that the thread is ready-to-run if the value reaches zero.

7. The parallel processing computer according to claim 5 , wherein each block of the synchronous control memory further has a lock flag, and wherein the plurality of thread executing unit supports both a lock instruction for locking the lock flag and a unlock instruction for unlocking the lock flag.

8. The parallel processing computer according to claim 1 , further comprising: at least one exclusive control thread capable of accessing at least one shared resource; an exclusion continuation controlling mechanism for controlling exclusion continuation to the at least one exclusive control thread; and exclusion access control means for controlling exclusion access to the at least one shared resource.

9. The parallel processing computer according to claim 6 , wherein each block of the synchronous control memory further has a lock flag, and wherein the plurality of thread executing unit supports both a lock instruction for locking the lock flag and a unlock instruction for unlocking the lock flag.