Method and Apparatus for a Shared I/O Serial Ata Controller

1. A shareable disk storage controller comprising: logic for coupling the controller to one or more storage devices, wherein the shareable disk storage controller is shared within the load-store architecture of a plurality of operating system domains; core logic, coupled to said logic, for managing data transfers to/from said one or more storage devices; and operating system domain identification logic, coupled to said core logic, for: receiving requests from the plurality of operating system domains; and determining which of the plurality of operating system domains is associated with each of said requests; wherein by determining which of the plurality of operating system domains is associated with each of said requests, the shareable disk storage controller supports requests from each of the plurality of operating system domains; wherein the load-store architecture comprises resources directly accessible by the plurality of operating system domains using load and/or store instructions, said resources comprising memory spaces for each of the plurality of operating system domains; and wherein upon initialization of the shareable disk storage controller by each of the plurality of operating system domains, a portion of said memory spaces for each of the plurality of operating system domains is allocated for communication to the shareable disk storage controller.

2. The shareable disk storage controller as recited in claim 1 wherein the shareable disk storage controller comprises a shareable SATA controller.

3. The shareable disk storage controller as recited in claim 1 wherein each of the plurality of operating system domains comprises: a processing complex; and memory, coupled to said processing complex.

4. The shareable disk storage controller as recited in claim 1 wherein said logic comprises: transport layer logic; link layer logic, coupled to said transport layer logic; and physical layer logic, coupled to said link layer logic, said physical layer logic providing the physical connection to at least one of said one or more storage devices.

5. The shareable disk storage controller as recited in claim 1 wherein said logic is coupled to said core logic for sending data between the shareable disk storage controller and said one or more storage devices.

6. The shareable disk storage controller as recited in claim 1 wherein said one or more storage devices comprise hard disks.

7. The shareable disk storage controller as recited in claim 6 wherein said hard disks comprise SATA disk drives.

8. The shareable disk storage controller as recited in claim 1 wherein said core logic further comprises: array control logic for managing two or more of said storage devices in an array configuration.

9. The shareable disk storage controller as recited in claim 8 wherein said array configuration comprises a RAID (Redundant Array of Inexpensive Disks) configuration.

10. The shareable disk storage controller as recited in claim 9 wherein said RAID configuration comprises: Raid levels 0, 1, 2, 3, 4, 5.

11. The shareable disk storage controller as recited in claim 1 wherein said core logic further comprises: a plurality of array control logic for managing two or more of said storage devices in an array configuration, for a plurality of the plurality of operating system domains.

12. The shareable disk storage controller as recited in claim 1 further comprising: one or more task files, coupled to said core logic, associated with the plurality of operating system domains supported by the shareable disk storage controller.

13. The shareable disk storage controller as recited in claim 12 wherein said one or more task files comprise: a task entry, having a task portion and an OSD portion.

14. The shareable disk storage controller as recited in claim 13 wherein said task portion holds a task defining work to be done by the controller, and said OSD portion stores an OSD identifier.

15. The shareable disk storage controller as recited in claim 14 wherein said OSD identifier associates said task with one of the plurality of operating system domains.

16. The shareable disk storage controller as recited in claim 12 wherein said one or more task files comprise: a first task file associated with a first one of the plurality of operating system domains; and a second task file associated with a second one of the plurality of operating system domains; wherein tasks originating from said first one of the plurality of operating system domains are stored in said first task file; and wherein tasks originating from said second one of the plurality of operating system domains are stored in said second task file.

17. The shareable disk storage controller as recited in claim 1 further comprising: one or more DMA (direct-memory-access) engines, coupled to said core logic, for use by said core logic to handle data transfers for the plurality of operating system domains.

18. The shareable disk storage controller as recited in claim 1 wherein said operating system domain identification logic is coupled to a multi-OSD aware load-store fabric.

19. The shareable disk storage controller as recited in claim 18 wherein said multi-OSD aware load store fabric comprises PCI-Express+.

20. The shareable disk storage controller as recited in claim 1 further comprising: a shared switch, coupled to said operating system domain identification logic, and coupled to a plurality of load-store fabrics, for receiving requests from said plurality of load-store fabrics and for presenting said requests to said operating system domain identification logic.

21. The shareable disk storage controller as recited in claim 20 wherein said plurality of load-store fabrics do not contain additional header information for identifying requests with one of the plurality of operating system domains.

22. The shareable disk storage controller as recited in claim 20 wherein said plurality of load-store fabrics comprise PCI-Express.

23. A Serial ATA (SATA) controller comprising: a plurality of interfaces, for coupling the controller to a plurality of disk drives; core logic, coupled to the plurality of interfaces, said core logic for managing requests for data transfers to/from said plurality of disk drives; and operating system domain identification logic (OSD ID), coupled to said core logic, for receiving requests from the plurality of processing complexes, and for determining for each of said received requests, which processing complex it is associated with; wherein the controller is shareable by the plurality of processing complexes, allowing each of the plurality of processing complexes to communicate with the controller within its own load-store architecture; wherein each load-store architecture of the plurality of processing complexes comprises resources directly accessible by the plurality of processing complexes using load and/or store instructions, said resources comprising memory spaces for each of the plurality of processing complexes; and wherein upon initialization of the controller by each of the plurality of processing complexes, a portion of said memory spaces for each of the plurality of processing complexes is allocated for communication to the controller.

24. The Serial ATA (SATA) controller as recited in claim 23 wherein each of the plurality of processing complexes comprise: one or more processing cores executing one or more operating systems; and memory, coupled to the one or more processing cores.

25. The Serial ATA (SATA) controller as recited in claim 23 wherein each of the plurality of processing complexes comprise: a processing core; and memory, coupled to the processing core.

26. The Serial ATA (SATA) controller as recited in claim 23 wherein each of the plurality of processing complexes utilizes PCI-Express as one of its load-store fabrics.

27. The Serial ATA (SATA) controller as recited in claim 23 wherein each of the plurality of processing complexes utilizes PCI-Express+ as one of its load-store fabrics.

28. The Serial ATA (SATA) controller as recited in claim 23 wherein said core logic further comprises array control logic, for managing one or more arrays among said plurality of disk drives.

29. The Serial ATA (SATA) controller as recited in claim 28 wherein said one or more arrays comprise RAID arrays.

30. The Serial ATA (SATA) controller as recited in claim 28 wherein said array control logic is configurable to provide a first array to support a first one of the plurality of processing complexes, and a second array to support a second one of the plurality of processing complexes.

31. The Serial ATA (SATA) controller as recited in claim 30 wherein said first array comprises a first set of the plurality of disk drives, and said second array comprises a second set of the plurality of disk drives.

32. The Serial ATA (SATA) controller as recited in claim 31 wherein said first set and said second set are physically distinct disk drives.

33. The Serial ATA (SATA) controller as recited in claim 31 wherein said first set and said second set are logically distinct disk drives, but are not necessarily physically distinct disk drives.

34. The Serial ATA (SATA) controller as recited in claim 32 wherein said OSD ID is coupled to an OSD aware load-store fabric.

35. The Serial ATA (SATA) controller as recited in claim 34 wherein said OSD aware load-store fabric comprises PCI-Express+.

36. The Serial ATA (SATA) controller as recited in claim 34 wherein said OSD aware load-store fabric comprises a load-store fabric that associates each packet with a particular one of the plurality of processing complexes.

37. The Serial ATA (SATA) controller as recited in claim 36 wherein the association is provided by adding header information to each packet.

38. The Serial ATA (SATA) controller as recited in claim 36 wherein the association is provided for each packet outside of said load-store fabric.

39. The Serial ATA (SATA) controller as recited in claim 23 further comprising: a shared switch, coupled to said OSD ID, and to the plurality of processing complexes, said shared switch for receiving packets from the plurality of processing complexes, and for associating each of said packets with the processing complex it is associated with.

40. The Serial ATA (SATA) controller as recited in claim 39 wherein said shared switch passes each of the packets, along with their association, to said OSD ID.

41. Serial ATA (SATA) controller as recited in claim 39 wherein said shared switch receives packets along with their association from said OSD ID, identifies which of the processing complexes the packets are associated with, and transmits the packets to their associated processing complex.

42. A computing environment comprising: at least one disk drive, coupled to a SATA controller; a shared switch, coupled between processing complexes and the SATA controller, the processing complexes comprising a first processing complex and a second processing complex, said shared switch associating each packet from the processing complexes with its originating processing complex, and forwarding said each packet, along with its association, to the SATA controller; the SATA controller comprising operating system domain identification logic (OSD ID) for receiving said each packet from said shared switch, for determining the association, and for processing said each packet for its associated processing complex; wherein the first processing complex and second processing complex share the SATA controller, the SATA controller communicating with each of the first and second processing complexes within its respective load-store domain; and wherein neither the first processing complex nor the second processing complex is necessarily aware that it is sharing the SATA controller; wherein the load-store domain comprises resources directly accessible by the plurality of processing complexes using load and/or store instructions, said resources comprising memory spaces for each of the processing complexes; and wherein upon initialization of the shareable disk storage controller by each of the processing complexes, a portion of said memory spaces for each of the processing complexes is allocated for communication to the storage controller.

43. The computing environment as recited in claim 42 wherein the first and second processing complexes each comprise: a processor; and memory coupled to said processor.

44. The computing environment as recited in claim 42 wherein the SATA controller, upon initialization by the first processing complex, communicates with the first processing complex utilizing memory within its load-store domain, and upon initialization by the second processing complex, communicates with the second processing complex utilizing memory within its load-store domain.

45. The computing environment as recited in claim 42 wherein said at least one disk drive is shared by the first and second processing complexes.

46. The computing environment as recited in claim 42 wherein the first and second processing complexes are coupled together to provide redundancy.

47. The computing environment as recited in claim 46 wherein the first processing complex utilizes said at least one disk drive, and the second processing complex utilizes a second disk drive.

48. The computing environment as recited in claim 47 wherein if either the first or second processing complex fails, the SATA controller makes both said at least one disk drive, and said second disk drive available to the non-failing processing complex.

49. The computing environment as recited in claim 42 wherein said shared switch resides on-chip with the first and second processing complexes.

50. The computing environment as recited in claim 42 wherein said shared switch resides on the SATA controller.

51. A serial ATA controller which is map-able to one or more processing complexes, the controller comprising: one or more interfaces to one or more disk drives; core logic, coupled to said one or more interfaces; and a load-store fabric interface, coupled to said core logic, for interfacing the controller to a load-store fabric that identifies packets with their associated processing complex, the load store fabric interface configurable to process packets from a first processing complex, said load-store fabric interface being reconfigurable to process packets from a second processing complex; the controller being shareable by the first processing complex and the second processing complex, allowing each of the first and second processing complexes to communicate with the controller within its own load-store architecture; wherein each load-store architecture of the processing complexes comprises resources directly accessible by the processing complexes using load and/or store instructions, said resources comprising memory spaces for each of the processing complexes; and wherein upon initialization of the controller by each of the processing complexes, a portion of said memory spaces for each of the processing complexes is allocated for communication to the controller.

52. The serial ATA controller as recited in claim 51 wherein said load-store fabric interface is reconfigurable without requiring said interface to be hard reset.

53. The serial ATA controller as recited in claim 51 wherein said hard reset requires re-powering said controller.

54. A method for sharing a serial ATA (SATA) controller by a plurality of processing complexes, the method comprising: initializing the SATA controller into the load-store resources of each of the plurality of processing complexes; associating packets from each of the plurality of processing complexes with their originating processing complex; transmitting the packets to the SATA controller; identifying for the SATA controller, which of the plurality of processing complexes is associated with the transmitted packets; processing each of the transmitted packets within SATA controller; and associating responses to said processing with their appropriate processing complex; and sharing the SATA controller by the plurality of processing complexes, allowing each of the plurality of processing complexes to communicate with the SATA controller within its own load-store architecture; wherein each load-store resource of the plurality of processing complexes comprises resources directly accessible by the plurality of processing complexes using load and/or store instructions, said resources comprising memory spaces for each of the plurality of processing complexes; and wherein upon initialization of the controller by each of the plurality of processing complexes, a portion of said memory spaces for each of the plurality of processing complexes is allocated for communication to the controller.

55. The method as recited in claim 54 wherein said initializing causes a driver within each of the processing complexes, that is associated with the SATA controller, to instantiate resource space into memory space of each of the plurality of processing complexes.

56. The method as recited in claim 54 wherein said step of associating packets from each of the plurality of processing complexes comprises adding header information which associates a packet with its upstream processing complex.

57. The method as recited in claim 56 wherein an associated packet contains header information, in addition to original packet information, so that the SATA controller can distinguish which packets are from which processing complex.