Hardware-Based Multi-Threading for Packet Processing

1. A method, comprising: buffering in an inbound buffer packet header and payload data corresponding to a plurality of inbound transmission control protocol (TCP) packets received at a destination machine; performing TCP input processing of the packet header and payload data that is buffered in the inbound buffer via a multi-threaded hardware engine, wherein multiple hardware-arbitrated threads are concurrently executed by the multi-threaded hardware engine to process the plurality of inbound TCP packets; performing a direct memory access (DMA) to concurrently transfer payload data buffered in the inbound buffer to a host memory while performing TCP input processing via the multi-threaded hardware engine; determining an existence of a TCP connection; generating TCP connection context data corresponding to the TCP connection; storing the TCP connection context data in the host memory; maintaining a cache in which selected TCP connection context data is cached; retrieving TCP connection context data for a given packet from one of the host memory and the cache; loading the retrieved TCP connection context data into a working register; and processing the TCP connection context data via the multi-threaded hardware engine to perform TCP input processing.

2. The method of claim 1 , further comprising arbitrating thread processing via a hardware-based scheduler.

3. The method of claim 2 , wherein arbitrating thread processing comprises performing at least one of thread suspension, thread scheduling, thread synchronizing, saving thread state and restoring thread state.

4. The method of claim 1 , wherein the multi-threaded hardware engine comprises a dedicated TCP offload engine (TOE).

5. The method of claim 1 , further comprising pre-posting memory locations in the host memory to which payload data is to be transferred.

6. The method of claim 1 , further comprising: performing a hash-based lookup against the cache to determine if the TCP connection context data for the given packet is present in the cache; and loading the TCP connection context data from the cache into the working register if the hash-based lookup results in a cache hit, otherwise copying the TCP connection context data from the host memory into the cache prior to loading the TCP connection data into the working register.

7. A method comprising: generating transmission control protocol (TCP) connection context data corresponding to a TCP connection employed to transmit payload data stored in a host memory from a host machine to a destination machine; performing TCP output processing of the payload data stored in memory via a multi-threaded hardware engine running on the host machine, wherein multiple hardware-arbitrated threads are concurrently executed by the engine to generate a plurality of outbound TCP packets containing the payload data, each outbound TCP packet including a header containing TCP connection data corresponding to the TCP connection context data; performing a direct memory access (DMA) transfer to concurrently transfer data comprising outbound TCP packets from host memory to a network interface controller (NIC) while performing TCP output processing via the multi-threaded hardware engine; maintaining a cache in which selected TCP connection context data is cached; retrieving the TCP connection context data for a given portion of payload data from one of the host memory and the cache; loading the TCP connection context data into a working register; processing the TCP connection context data via the multi-threaded hardware engine to perform TCP output processing; performing a hash-based lookup against the cache to determine if the TCP connection context data for the given portion of payload data is present in the cache; and loading the TCP connection context data from the cache into the working register if the hash-based lookup results in a cache hit, otherwise copying the TCP connection context data from host memory into the cache prior to loading the TCP connection data into the working register.

8. The method of claim 7 , further comprising arbitrating thread processing via a hardware-based scheduler.

9. The method of claim 8 , wherein arbitrating thread processing comprises performing at least one of thread suspension, thread scheduling, thread synchronizing, saving thread state and restoring thread state.

10. The method of claim 7 , wherein the multi-threaded hardware engine comprises a dedicated TCP offload engine (TOE).

11. The method of claim 7 , further comprising maintaining a DMA transmit queue containing information defining how DMA transfers are queued.

12. An integrated circuit, comprising: a multi-threaded transmission control protocol (TCP) offload engine (TOE), including: a processing engine having: a pipelined arithmetic logic unit (ALU); a working register, communicatively coupled to the pipelined ALU; an instruction cache to store instructions executable by the pipelined ALU; and an instruction register, communicatively coupled between the instruction cache and the pipelined ALU; a scheduler, communicatively coupled to the processing engine; a host memory interface, communicatively coupled to the processing engine; and a network interface controller (NIC) interface; communicatively coupled to the processing engine; and a direct memory access (DMA) controller, communicatively coupled to the NIC interface and the host memory interface.

13. The integrated circuit of claim 12 , further comprising a cache communicatively coupled to the processing engine and the host memory interface.

14. The integrated circuit of claim 12 , further comprising a host interface communicatively coupled to the processing engine.

15. The integrated circuit of claim 12 , wherein the processing engine further includes a thread cache, communicatively coupled to the working register.

16. The integrated circuit of claim 12 , wherein the integrated circuit comprises a memory controller hub (MCH) in a platform chipset.

17. A system, comprising: at least one processor, communicatively coupled to a frontside bus; host memory communicatively coupled to a memory bus; and a memory controller hub (MCH) communicatively coupled to the at least one processor via the frontside bus and the host memory via the memory bus, the MCH embodied as an integrated circuit comprising: a multi-threaded transmission control protocol (TCP) offload engine (TOE), including: a processing engine; a scheduler, communicatively coupled to the processing engine; a host memory interface, communicatively coupled to the processing engine and the memory bus; a host interface, communicatively coupled to the processing engine and the frontside bus; a network interface controller (NIC) interface; communicatively coupled to the processing engine; and a direct memory access (DMA) controller, communicatively coupled to the NIC interface and the host memory interface.

18. The system of claim 17 , further comprising a network interface controller (NIC), communicatively coupled to the NIC interface via one of a PCI (peripheral component interconnect) or PCI-X (PCI Express) bus.

19. The system of claim 17 , wherein the MCH further includes a cache communicatively coupled to the processing engine and the host memory interface.